void __2_1__General_Description() {
    /**
     * @group:       	2.1 General Description
     *
     * @description: 	The KSZ9477S is a highly-integrated, IEEE 802.3 compliant networking device that incorporates a layer-2 managed
     * 					Gigabit Ethernet switch, five 10BASE-Te/100BASE-TX/1000BASE-T physical layer transceivers (PHYs) and associated
     * 					MAC units, and two individually configurable MAC ports (one SGMII interface, one RGMII/MII/RMII interface) for direct
     * 					connection to a host processor/controller, another Ethernet switch, or an Ethernet PHY transceiver. The SGMII port has
     * 					two modes of operation: SerDes mode (which supports 1000BASE-X fiber) and SGMII mode.
     * 					The KSZ9477S is built upon industry-leading Ethernet technology, with features designed to offload host processing
     * 					and streamline the overall design:
     * 					• Non-blocking wire-speed Ethernet switch fabric supports 1 Gbps on RGMII
     * 					• Full-featured forwarding and filtering control, including port-based Access Control List (ACL) filtering
     * 					• Full VLAN and QoS support
     * 					• Traffic prioritization with per-port ingress/egress queues and by traffic classification
     * 					• Spanning Tree support
     * 					• IEEE 802.1X access control support
     * 					As a member of the EtherSynch product family, the KSZ9477S incorporates full hardware support for the IEEE 1588v2
     * 					Precision Time Protocol (PTP), including hardware time-stamping at all PHY-MAC interfaces, and a high-resolution
     * 					hardware “PTP clock”. IEEE 1588 provides sub-microsecond synchronization for a range of industrial Ethernet applica-
     * 					tions.
     * 					The KSZ9477S fully supports the IEEE family of Audio Video Bridging (AVB) standards, which provides high Quality of
     * 					Service (QoS) for latency sensitive traffic streams over Ethernet. Time-stamping and time-keeping features support
     * 					IEEE 802.1AS time synchronization. All ports feature credit based traffic shapers for IEEE 802.1Qav, and a time aware
     * 					scheduler as proposed for IEEE 802.1Qbv.
     * 					The KSZ9477S also incorporates features that simplify the implementation of DLR and HSR redundancy protocols by
     * 					offloading tasks from the host processor. For DLR networks, these features include Beacon frame generation, Beacon
     * 					timeout detection, and MAC table flushing. HSR networks are supported with automatic duplicate frame discard and
     * 					self-address filtering.
     * 					The 100Mbps PHYs feature Quiet-WIRE internal filtering to reduce line emissions and enhance immunity to environ-
     * 					mental noise. It is ideal for automotive or industrial applications where stringent radiated emission limits must be met.
     * 					A host processor can access all KSZ9477S registers for control over all PHY, MAC, and switch functions. Full register
     * 					access is available via the integrated SPI or I 2C interfaces, and by in-band management via any one of the data ports.
     * 					PHY register access is provided by a MIIM interface. Flexible digital I/O voltage allows the MAC port to interface directly
     * 					with a 1.8/2.5/3.3V host processor/controller/FPGA.
     * 					Additionally, a robust assortment of power-management features including Wake-on-LAN (WoL) for low power standby
     * 					operation, have been designed to satisfy energy-efficient system requirements.
     * 					The KSZ9477S is available in an industrial (-40°C to +85°C) temperature range. An internal block diagram of the
     * 					KSZ9477S is shown in Figure 2-1.
     *
     *
     * 					====================================================
     * 					FIGURE 2-1: INTERNAL BLOCK DIAGRAM - KSZ9477S
     * 					====================================================
     *
     * 					Ports & PHYs (1-5):
     * 					-------------------
     * 					*   5x 10/100/1000 PHYs (Physical Layer Transceiver)
     * 					*   Ports 1-5 leiten zu internen GMACs 1-5.
     * 					*   IEEE 1588/802.1AS Time Stamp Funktionalität ist integriert.
     *
     * 					Switch Engine:
     * 					--------------
     * 					*   Verbindet interne GMACs (1-5) mit externen GMACs (6, 7).
     * 					*   Beinhaltet 1588 & AVB Processing, Queue Management (QOS), etc.
     * 					*   Interne Komponenten: Address Lookup, MIB Counters, Frame Buffers, Queue Management.
     *
     * 					Schnittstellen (Extern):
     * 					-----------------------
     * 					*   Port 6/7: RGMII/MII/RMII und SGMII Schnittstellen.
     * 					*   Management: SPI/I2C/MIIM Interface, Control Registers.
     *
     * 					Zeitstempel & GPIO:
     * 					-------------------
     * 					*   IEEE 1588/802.1AS Clock für Precision GPIO und internes Timing.
     * 					*   General Purpose Input/Output (GPIO) Pin.
     *
     */
}