void __3_2__Pin_Descriptions() { /** * @group: 3.2 Pin Descriptions * * @description: This sections details the functions of the various device signals. * * * TABLE 3-2: PIN DESCRIPTIONS * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Name | Symbol | Buffer | Description | * | | | Type | | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Ports 5-1 Gigabit Ethernet Pins | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5-1 Ethernet TX/RX | TXRX[5:1]P_A | AIO | Port 5-1 1000BASE-T Differential Data Pair A (+) | * | Pair A + | | | Note: 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5-1 Ethernet TX/RX | TXRX[5:1]M_A | AIO | Port 5-1 1000BASE-T Differential Data Pair A (-) | * | Pair A - | | | Note: 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5-1 Ethernet TX/RX | TXRX[5:1]P_B | AIO | Port 5-1 1000BASE-T Differential Data Pair B (+) | * | Pair B + | | | Note: 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5-1 Ethernet TX/RX | TXRX[5:1]M_B | AIO | Port 5-1 1000BASE-T Differential Data Pair B (-) | * | Pair B - | | | Note: 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5-1 Ethernet TX/RX | TXRX[5:1]P_C | AIO | Port 5-1 1000BASE-T Differential Data Pair C (+) | * | Pair C + | | | | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5-1 Ethernet TX/RX | TXRX[5:1]M_C | AIO | Port 5-1 1000BASE-T Differential Data Pair C (-) | * | Pair C - | | | | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5-1 Ethernet TX/RX | TXRX[5:1]P_D | AIO | Port 5-1 1000BASE-T Differential Data Pair D (+) | * | Pair D + | | | | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5-1 Ethernet TX/RX | TXRX[5:1]M_D | AIO | Port 5-1 1000BASE-T Differential Data Pair D (-) | * | Pair D - | | | | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 RGMII/MII/RMII Pins | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Transmit/Reference | TX_CLK6/ | I/O8 | MII Mode: TX_CLK6 is the Port 6 25/2.5MHz Transmit Clock. In PHY mode this pin is an output, in MAC mode it is an | * | Clock | REFCLKI6 | | input. | * | | | | RMII Mode: REFCLKI6 is the Port 6 50MHz Reference Clock input when in RMII Normal mode. This pin is unused when in | * | | | | RMII Clock mode. | * | | | | RGMII Mode: TX_CLK6 is the Port 6 125/25/2.5MHz Transmit Clock input. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Transmit | TX_EN6/ | IPD | MII/RMII Modes: TX_EN6 is the Port 6 Transmit Enable. | * | Enable/Control | TX_CTL6 | | RGMII Mode: TX_CTL6 is the Port 6 Transmit Control. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Transmit Error | TX_ER6 | IPD | MII Mode: Port 6 Transmit Error input. | * | | | | RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Collision Detect | COL6 | IPD/O8 | MII Mode: Port 6 Collision Detect. In PHY mode this pin is an output, in MAC mode it is an input. | * | | | | RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Transmit Data 3 | TXD6_3 | IPD | MII/RGMII Modes: Port 6 Transmit Data bus bit 3. | * | | | | RMII Mode: Not used. Do not connect this pin in this mode of operation. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Transmit Data 2 | TXD6_2 | IPD | MII/RGMII Modes: Port 6 Transmit Data bus bit 2. | * | | | | RMII Mode: Not used. Do not connect this pin in this mode of operation. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Transmit Data 1 | TXD6_1 | IPD | MII/RMII/RGMII Modes: Port 6 Transmit Data bus bit 1. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Transmit Data 0 | TXD6_0 | IPD | MII/RMII/RGMII Modes: Port 6 Transmit Data bus bit 0. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Receive/Reference | RX_CLK6/ | IPD/O24 | MII Mode: RX_CLK6 is the Port 6 25/2.5MHz Receive Clock. In PHY mode this pin is an output, in MAC mode it is an | * | Clock | REFCLKO6 | | input. | * | | | | RMII Mode: REFCLKO6 is the Port 6 50MHz Reference Clock output when in RMII Clock mode. This pin is unused when in | * | | | | RMII Normal mode. | * | | | | RGMII Mode: RX_CLK6 is the Port 6 125/25/2.5MHz Receive Clock output. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Receive Data Valid/ | RX_DV6/ | IPD/O24 | MII Mode: RX_DV6 is the Port 6 Received Data Valid output. | * | Carrier Sense / Control | CRS_DV6/ | | RMII Mode: CRS_DV6 is the Carrier Sense / Receive Data Valid output. | * | | RX_CTL6 | | RGMII Mode: RX_CTL6 is the Receive Control output. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Receive Error | RX_ER6 | IPD/O24 | MII Mode: Port 6 Receive Error output. | * | | | | RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Carrier Sense | CRS6 | IPD/O8 | MII Mode: Port 6 Carrier Sense. In PHY mode this pin is an output, in MAC mode it is an input. | * | | | | RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Receive Data 3 | RXD6_3 | I/O24 | MII/RGMII Modes: Port 6 Receive Data bus bit 3 output. | * | | | | RMII Mode: Not used. Do not connect this pin in this mode of operation. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Receive Data 2 | RXD6_2 | I/O24 | MII/RGMII Modes: Port 6 Receive Data bus bit 2 output. | * | | | | RMII Mode: Not used. Do not connect this pin in this mode of operation. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Receive Data 1 | RXD6_1 | I/O24 | MII/RMII/RGMII Modes: Port 6 Receive Data bus bit 1 output. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 Receive Data 0 | RXD6_0 | I/O24 | MII/RMII/RGMII Modes: Port 6 Receive Data bus bit 0 output. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 6 I/O Power Supply | VDDIO | Vdd | Port 6 I/O Power Supply (1.8V/2.5V/3.3V). | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | PME_N | PME_N | IPU | Power Management Event active low output. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | INTRP_N | INTRP_N | IPU | Interrupt active low output. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | SYNCLKO | SYNCLKO | O8 | Synchronous Clock output (programmable). | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | RESET_N | RESET_N | IPU | Global Reset active low input. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Ports 4-1 Gigabit Ethernet Pins | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 4-1 Ethernet TX/RX | TXRX[4:1]P_A | AIO | Port 4-1 1000BASE-T Differential Data Pair A (+) | * | Pair A + | | | Note: 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | SPI Data In / I2C/MIIM | SDI/SDA/MDIO | IPU/O8 | SPI Mode: SDI Data In (also known as MOSI). | * | Data In/Out | | | I2C Mode: SDA Data In/Out. | * | | | | MIIM Mode: MDIO Data In/Out. | * | | | | SDI and MDIO are open-drain signals when in the output state. An external pull-up resistor to VDDIO (1.0kΩ to | * | | | | 4.7kΩ) is required. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | SPI Chip Select | SCS_N | IPU | SPI Mode: Chip Select (active low). | * | | | | I2C/MIIM Modes: Not used. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | LED Pins | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 1 LED Indicator 0 | LED1_0 | IPU/O8 | Port 1 LED Indicator 0. Active low output sinks current to light an external LED. Note: This pin also provides | * | | | | configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for | * | | | | additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 1 LED Indicator 1 | LED1_1 | IPU/O8 | Port 1 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides | * | | | | configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for | * | | | | additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 2 LED Indicator 0 | LED2_0 | IPU/O8 | Port 2 LED Indicator 0. Active low output sinks current to light an external LED. Note: This pin also provides | * | | | | configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for | * | | | | additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 2 LED Indicator 1 | LED2_1 | IPU/O8 | Port 2 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides | * | | | | configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for | * | | | | additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 3 LED Indicator 0 | LED3_0 | IPU/O8 | Port 3 LED Indicator 0. Active low output sinks current to light an external LED. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 3 LED Indicator 1 | LED3_1 | IPU/O8 | Port 3 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides | * | | | | configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for | * | | | | additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 4 LED Indicator 0 | LED4_0 | IPU/O8 | Port 4 LED Indicator 0. Active low output sinks current to light an external LED. Note: This pin also provides | * | | | | configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for | * | | | | additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 4 LED Indicator 1 | LED4_1 | IPU/O8 | Port 4 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides | * | | | | configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for | * | | | | additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5 LED Indicator 0 | LED5_0 | IPU/O8 | Port 5 LED Indicator 0. Active low output sinks current to light an external LED. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Port 5 LED Indicator 1 | LED5_1 | IPU/O8 | Port 5 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides | * | | | | configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for | * | | | | additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Miscellaneous Pins | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Interrupt | INTRP_N | OPU | Active low, open-drain interrupt. This pin also provides configuration strap functions during hardware/software | * | | | | resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Note: This pin requires an | * | | | | external pull-up resistor. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Power Management Event | PME_N | O8 | Power Management Event. This output signal indicates that an energy detect event has occurred. It is intended to | * | | | | wake up the system from a low power mode. Note: The assertion polarity is programmable (default active low). An | * | | | | external pull-up resistor is required for active-low operation; an external pull-down resistor is required for | * | | | | active-high operation. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | System Reset | RESET_N | IPU | Active low system reset. The device must be reset either during or after power-on. An RC circuit is suggested for | * | | | | power-on reset. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Crystal Clock / Oscillator | XI | ICLK | Crystal clock / oscillator input. When using a 25MHz crystal, this input is connected to one lead of the crystal. | * | Input | | | When using an oscillator, this pin is the input from the oscillator. The crystal oscillator should have a | * | | | | tolerance of ±50ppm. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Crystal Clock Output | XO | OCLK | Crystal clock / oscillator output. When using a 25MHz crystal, this output is connected to one lead of the crystal. | * | | | | When using an oscillator, this pin is left unconnected. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | 25/125MHz Reference Clock | SYNCLKO | IPU/O24 | 25/125MHz reference clock output, derived from the crystal input or the recovered clock of any PHY. This signal | * | Output | | | may be used for Synchronous Ethernet. This pin also provides configuration strap functions during hardware/ | * | | | | software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | General Purpose | GPIO_1 | IPU/O8 | This signal can be used as an input or output for use by the IEEE 1588 event trigger or timestamp capture units. | * | Input/Output 1 | | | It will be synchronized to the internal IEEE 1588 clock. This pin can also be controlled (as an output) or sampled | * | | | | (as an input) via device registers. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Transmit Output Current Set| ISET | A | Transmit output current set resistor. This pin configures the physical transmit output current. It must be | * | Resistor | | | connected to GND through a 6.04kΩ 1% resistor. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | In-Band Management | IBA | IPD | In-Band Management Configuration strap. This pin provides configuration strap functions during hardware/software | * | Configuration Strap | | | resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | No Connect | NC | - | No Connect. For proper operation, this pin must be left unconnected. | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Power/Ground Pins | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | +3.3/2.5/1.8V I/O Power | VDDIO | P | +3.3V / +2.5V / +1.8V I/O Power | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | +2.5V Analog Power | AVDDH | P | +2.5V Analog Power | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | +1.2V Analog Power | AVDDL | P | +1.2V Analog Power | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | +1.2V Digital Power | DVDDL | P | +1.2V Digital Power | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | +1.2V SGMII Core Power | VDDLS | P | +1.2V SGMII Core Power | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | +2.5V SGMII I/O Power | VDDHS | P | +2.5V SGMII I/O Power | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * | Ground | GND | GND | Ground (pins and pad) | * +----------------------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------+ * */ }