void __4_10__Power() {
    /**
     * @group:       	4.10 Power
     *
     * @description: 	The KSZ9477S requires two to three supply voltages. The device core operates from a 1.2V supply (DVDDL and
     * 					AVDDL). The PHY transceivers and XI/XO crystal/clock interface operate from a 2.5V supply (AVDDH). The digital I/
     * 					O's can be operated from 1.8V, 2.5V or 3.3V (VDDIO). The digital I/Os powered from VDDIO include RGMII, RMII, MII,
     * 					SPI, I2 C, MIIM, LED, RESET_N, PME_N, INTRP_N and SYNCLKO. The SGMII interface requires 2.5V (VDDHS) and
     * 					1.2V (VDDLS) supplies. An example power connection diagram can be seen in Figure 4-10.
     *
     *					======================================
     *					POWER CONNECTION DIAGRAM OVERVIEW
     *					======================================
     *
     *					Chip Power Domains:
     *					-------------------
     *					- VDDLS: Core logic supply, typically derived from +1.2V input via filter.
     *					- DVDDL: Digital I/O supply.
     *					- AVDDL: Analog I/O supply.
     *					- AVDDH: High voltage analog supply (+2.5V input).
     *					- VDDHS: High speed digital supply (+1.8V/2.5V/3.3V input).
     *					- VDDIO: Input/Output supply (+1.8V/2.5V/3.3V input).
     *
     *					Filtering Components (Typical per rail):
     *					----------------------------------------
     *					- Inductors (Spulen): 22µF (approx.) for isolation/filtering.
     *					- Decoupling Capacitors (Kondensatoren): Primarily 0.1µF and some 22µF/10µF bulk caps.
     *
     *					Grounding:
     *					---------
     *					- Multiple GND pins are connected together.
     *					- Exposed Pad GND connection is crucial.
     *
     */
}