void __4_12_1__SPI_SLAVE_BUS() {
    /**
     * @group:       	4.12.1 SPI SLAVE BUS
     *
     * @description:	The KSZ9477S supports a slave mode SPI interface that provides complete access to all device registers via an SPI
     *					master device. The SPI master device supplies the clock (SCL), select (SCS_N), and serial input data (SDI). Serial out-
     *					put data (SDO) is driven by the KSZ9477S.
     *					SCL is expected to stay low when SPI operation is idle. SPI operations start with the falling edge of SCS_N and end with
     *					the rising edge of SCS_N. A single read or write access consists of a 27-bit command/address phase, then a 5-bit turn-
     *					around (TA) phase, then an 8-bit data phase. For burst read or write access, SCS_N is held low while SCL continues to
     *					toggle. For every 8 cycles of SCL, the device will increment the address counter, and the corresponding data byte will
     *					be transferred on SDI or SDO in succession.
     *					All commands, addresses and data are transferred most significant bit first. Input data on SDI is latched on the rising
     *					edge of clock SCL. Output data on SDO is clocked on the falling edge of SCL.
     *					As shown in Figure 4-26, there are two commands: register read and register write. Figure 4-11 and Figure 4-12 show
     *					the timing for these two operations.
     *
     *
     *					TABLE 4-26: REGISTER ACCESS USING THE SPI INTERFACE
     *					+----------------+-------------------------------------------------------------+---------------------+
     *					| SPI Operation  | Command/Address Phase (SDI pin)                             | Data Phase          |
     *					| (Note 4-8)     +------------+---------------------------------+--------------+ (SDO or SDI pins)   |
     *					|                | Command    | Register Address                | TA bits      |                     |
     *					|                | 		      | 				                | (Note 4-8)   |                     |
     *					+----------------+------------+---------------------------------+--------------+---------------------+
     *					| Register Read  | 011        | A23...A0                        | XXXXX        | D7...D0             |
     *					+----------------+------------+---------------------------------+--------------+---------------------+
     *					| Register Write | 010        | A23...A0                        | XXXXX        | D7...D0             |
     *					+----------------+------------+---------------------------------+--------------+---------------------+
     *					Note 4-8 TA bits are turn-around bits. They are “don't care” bits.
     *
     *					     * @note:			The actual device address space is 16 bits (A15 - A0), so the values of address bits A23 - A16 in the SPI
     *					command/address phase are “don't care”.
     *
     *
     *					===========================================
     *					FIGURE 4-11: SPI REGISTER READ OPERATION
     *					===========================================
     *
     *					DIAGRAMM-SEQUENZ (TAKTE 1-40):
     *					------------------------------
     *
     *					PHASE 1: Read Command (Takte 1-3)
     *					----------------------------------
     *					*   SCS_N: Low (aktiv)
     *					*   SCL: Taktet
     *					*   SDI (MOSI): Sendet den Lese-Befehl (011)
     *
     *					PHASE 2: Read Address (Takte 4-27)
     *					----------------------------------
     *					*   SCS_N: Low
     *					*   SCL: Taktet
     *					*   SDI (MOSI): Sendet die 24-Bit-Adresse (A23 bis A0)
     *
     *					PHASE 3: TurnAround (Takte 28-32)
     *					----------------------------------
     *					*   SCS_N: Low
     *					*   SCL: Taktet
     *					*   SDI (MOSI): Daten irrelevant (TA/XXXXX)
     *					*   SDO (MISO): Bus wird vom Slave übernommen (High-Z zu aktiv)
     *
     *					PHASE 4: Read Data (Takte 33-40)
     *					--------------------------------
     *					*   SCS_N: Low, dann High (deaktiviert)
     *					*   SCL: Taktet
     *					*   SDO (MISO): Sendet die 8-Bit-Lesedaten (D7 bis D0)
     *
     *
     *					===========================================
     *					FIGURE 4-12: SPI REGISTER WRITE OPERATION
     *					===========================================
     *
     *					DIAGRAMM-SEQUENZ (TAKTE 1-40):
     *					------------------------------
     *
     *					PHASE 1: Write Command (Takte 1-3)
     *					----------------------------------
     *					*   SCS_N: Low (aktiv)
     *					*   SCL: Taktet
     *					*   SDI (MOSI): Sendet den Schreib-Befehl (010)
     *
     *					PHASE 2: Write Address (Takte 4-27)
     *					----------------------------------
     *					*   SCS_N: Low
     *					*   SCL: Taktet
     *					*   SDI (MOSI): Sendet die 24-Bit-Adresse (A23 bis A0)
     *
     *					PHASE 3: TurnAround (Takte 28-32)
     *					----------------------------------
     *					*   SCS_N: Low
     *					*   SCL: Taktet
     *					*   SDI (MOSI): Daten irrelevant (TA/XXXXX)
     *					*   SDO (MISO): Bleibt Hi-Z, da es eine Schreiboperation ist.
     *
     *					PHASE 4: Write Data (Takte 33-40)
     *					--------------------------------
     *					*   SCS_N: Low, dann High (deaktiviert)
     *					*   SCL: Taktet
     *					*   SDI (MOSI): Sendet die 8-Bit-Schreibdaten (D7 bis D0)
     *					*   SDO (MISO): Bleibt Hi-Z.
     *
     */
}