void __4_12_2__I2C_BUS() {
    /**
     * @group:       	4.12.2 I2 C BUS
     *
     * @description:	The management interface may be configured to be an I 2
     *					C slave. In this mode, an I2 C master has complete program-
     *					ming access to the device's internal control and status registers, including all MIB counters, address lookup tables,
     *					VLAN table and ACL table.
     *					The 7-bit device address is fixed as 1011_111. Because of the fixed address, only one KSZ9477S may be on the I 2 C
     *					bus at a time. The R/W control bit is then appended as the least significant bit to form these 8-bit address/control words:
     *
     *					1011_1110 <write>
     *					1011_1111 <read>
     *
     *					The internal registers and tables of the device are accessed using 16-bit addressing and 8-bit data. The access formats
     *					are as follows:
     *
     *					FIGURE 4-13: SINGLE BYTE REGISTER WRITE
     *					+---+----------+---+---+-----------+---+-----------+---+----------+---+---+
     *					| S | Slave    | W | A | Addr[15:8]| A | Addr[7:0] | A | Data[7:0]| A | P |
     *					|   | Addr[6:0]|   |   |           |   |           |   |          |   |   |
     *					+---+----------+---+---+-----------+---+-----------+---+----------+---+---+
     *					<------------------- From master to slave ---------------------------------->
     *					<--- From slave to master ------------------------------------------------->
     *
     *					Legende:
     *					A : Acknowledge,
     *					/A : not Acknowledge
     *
     *
     *					FIGURE 4-14: SINGLE BYTE REGISTER READ
     *					+---+-----------+---+---+-----------+---+-----------+---+---+-----------+---+----------+---+---+---+
     *					| S | Slave     | W | A | Addr[15:8]| A | Addr[7:0] | A | S | Slave     | R | A | Data[7:0]|/A | P |
     *					|   | Addr[6:0] |   |   |           |   |           |   |   | Addr[6:0] |   |   |          |   |   |
     *					+---+-----------+---+---+-----------+---+-----------+---+---+-----------+---+----------+---+---+---+
     *
     *
     *					FIGURE 4-15: BURST REGISTER WRITE
     *					+---+----------+---+---+-----------+---+-----------+---+----------+---+-----+----------+---+---+
     *					| S | Slave    | W | A | Addr[15:8]| A | Addr[7:0] | A | Data[7:0]| A | ... | Data[7:0]| A | P |
     *					|   | Addr[6:0]|   |   |           |   |           |   |          |   |     |          |   |   |
     *					+---+----------+---+---+-----------+---+-----------+---+----------+---+-----+----------+---+---+
     *					<------------------- From master to slave ---------------------------------->
     *					<--- From slave to master ------------------------------------------------->
     *
     *					Legende:
     *					A : Acknowledge
     *					/A : not Acknowledge
     *					...: repeat Data[7:0] & A.
     *
     *
     *					FIGURE 4-16: BURST REGISTER READ
     *					+---+-----------+---+---+-----------+---+-----------+---+---+-----------+---+---+-----------+---+-----+
     *					| S | Slave     | W | A | Addr[15:8]| A | Addr[7:0] | A | S | Slave     | R | A | Data[7:0] | A | ... |
     *					|   | Addr[6:0] |   |   |           |   |           |   |   | Addr[6:0] |   |   |           |   |     |
     *					+---+-----------+---+---+-----------+---+-----------+---+---+-----------+---+---+-----------+---+-----+
     *
     *					                                                                                       +-----------+---+---+
     *					                                                                                       | Data[7:0] |/A | P |
     *					                                                                                       +-----------+---+---+
     *					<------------------------------ From master to slave ----------------------------------------->
     *					<-------------------------------------- From slave to master --------------------------------->
     *
     *					Legende:
     *					A : Acknowledge
     *					/A : not Acknowledge
     *					...: repeat Data[7:0] & /A.
     *
     */
}