void __4_12_3__MII_MANAGEMENT_MIIM_INTERFACE() {
    /**
     * @group:       	4.12.3 MII MANAGEMENT (MIIM) INTERFACE
     *
     * @description:	The device supports the IEEE 802.3 MII management interface, also known as the management data input/output
     *					(MDIO) interface. This interface allows upper-layer devices to monitor and control the states of the KSZ9477S PHY
     *					blocks, but it does not provide access to the switch registers. An external device with MDC/MDIO capability can read
     *					the PHY status or configure the PHY settings. Details on the MIIM interface can be found in Clauses 22 and 45 of the
     *					IEEE 802.3 Specification.
     *					Use of MIIM conflicts with use of the In-Band Management interface. These interfaces cannot be used simultaneously.
     *					The MIIM interface consists of the following:
     *					• A physical connection that uses a data signal (MDIO) and a clock signal (MDC) for communication between an
     *					external controller and the KSZ9477S. Note that the MDIO signal is open-drain.
     *					• A specific protocol that operates across the two signal physical connection that allows an external controller to
     *					communicate with the internal PHY devices.
     *					• Access to a set of standard, vendor-specific and extended (MMD) 16-bit registers. These registers are also
     *					directly accessible via the SPI and I 2 C interface options.
     *					The MIIM Interface can operate up to a maximum clock speed of 5MHz. Access is limited to only the registers in the
     *					PHY blocks of ports 1 through 5. Table 4-27 summarizes the MII management interface frame format.
     *
     *
     *					TABLE 4-27: MII MANAGEMENT INTERFACE FRAME FORMAT
     *					+-----------+------------+------------+-----------+------------+------------+------------+------------+------+
     *					| Operation | Preamble   | Start of   | Operation | PHY        | Register   | Turn       | Register   | Idle |
     *					| Mode      | (32-bit)   | Frame      | Code      | Address    | Address    | Around     | Data       |      |
     *					|           |            | (2-bit)    | (2-bit)   | (5-bit)    | (5-bit)    | (2-bit)    | (16-bit)   |      |
     *					+-----------+------------+------------+-----------+------------+------------+------------+------------+------+
     *					| Read      | All 1s     | 01         | 10        | A[4:0]     | Reg[4:0]   | Z0         | D[15:0]    | Z    |
     *					+-----------+------------+------------+-----------+------------+------------+------------+------------+------+
     *					| Write     | All 1s     | 01         | 01        | A[4:0]     | Reg[4:0]   | 10         | D[15:0]    | Z    |
     *					+-----------+------------+------------+-----------+------------+------------+------------+------------+------+
     *
     *					The MIIM PHY address to PHY port mapping is as follows:
     *					• PHY Address 1h to PHY port 1
     *					• PHY Address 2h to PHY port 2
     *					• PHY Address 3h to PHY port 3
     *					• PHY Address 4h to PHY port 4
     *					• PHY Address 5h to PHY port 5
     *					The MIIM register address space consists of two distinct areas.
     *					• Standard MIIM Registers (Direct)
     *					• MDIO Manageable Device (MMD) Registers (Indirect)
     *
     */
}