void __4_13__In_Band_Management() {
    /**
     * @group:       	4.13 In-Band Management
     *
     * @description:	The in-band management access (IBA) is a feature that provides full register read and write access via any one of the
     *					seven data ports. Port 7 is the default IBA port. The in-band feature is enabled or disabled by a strapping option at
     *					power-up and reset. To use a different port instead of port 7 for IBA, the SPI or I2 C interface or IBA must be used to
     *					write to a control register. IBA may not be used on more than one port at a time, but the IBA port cans till be used for
     *					sending and receiving non-IBA traffic.
     *					In-band management frames are processed differently from normal network frames. They are recognized as special
     *					frames, so address and VID lookup, VLAN tagging, source address filtering, un-tag discard, tagged frame drop, etc. are
     *					not applied to them. Received in-band management frames are never forwarded to the switch fabric or to any other port..
     *					The In-Band Management (IBA) Control Register is used to enable and control the IBA feature and to specify one of the
     *					seven ports as the IBA port.
     *					The IBA frame format is shown in Figure 4-17. The layer 2 portion of the IBA frame contains normal destination address
     *					(DA) and source address (SA) fields. The DA of the frames are defined to be the switch MAC address (default 00-10-
     *					A1-FF-FF-FF), and the SA is the MAC address of the source device. The DA and SA will be swapped in the response
     *					frame. A special 4-byte IBA tag follows the SA. This is then followed by the 2-byte EtherType/Length field that serves to
     *					identify this as an IBA frame.
     *					Only one IBA frame can be processed at a time. Any subsequent IBA frames received by the device will be dropped
     *					unless the most recent response frame has been fully transmitted.
     *					There are six types of read/write commands: READ, WRITE, WAIT on 0, WAIT on 1, MODIFY to 0 and MODIFY to 1.
     *					The minimum IBA read or write size is 32 bits. There is no IBA option for 8-bit or 16-bit transfers.
     *					The burst commands offer fast and bundled data return, up to the capacity of the IBA frame buffer. There are two types
     *					of operations in burst command: READ burst and Write burst.
     *
     *
     *					================================================================================
     *					FIGUR 4-17: IN-BAND MANAGEMENT FRAME FORMAT
     *					================================================================================
     *
     *					 LSB 0 1 2 3 4 5 6 7 MSB
     *
     *					+-----------+
     *					| PREAMBLE  | 7 Bytes
     *					+-----------+
     *					| SFD       | 1 Byte (11111110)
     *					+-----------+
     *					| DES. ADDR | 6 Bytes (I/G, U/L, 46 bit address)
     *					+-----------+
     *					| SRC. ADDR | 6 Bytes (I/G, U/L, 46 bit address)
     *					+-----------+
     *					| MAC       | 2 Bytes
     *					| LENGTH/TYPE|
     *					+-----------+
     *
     *					--------------------------------------------------------------------------------
     *					IBAF TAG (Optional)
     *					--------------------------------------------------------------------------------
     *
     *					+-----------+
     *					| IBAF TAG  | 2 Bytes (TPID: 0x9800 for 98xx Family)
     *					| TYPE      |
     *					+-----------+
     *					| IBAF TAG  | 2 Bytes (3 bits Priority, 1 bit CFI=0, 4 bits Mode, 8 bits Seq #)
     *					| CONTROL INFO.|
     *					+-----------+
     *
     *					--------------------------------------------------------------------------------
     *					IBAF LAYER 3 DATA / MAC DATA
     *					--------------------------------------------------------------------------------
     *
     *					+-----------+
     *					| ACCESS    | 2 Bytes (0x0000)
     *					| FORMAT    |
     *					+-----------+
     *					| Reserved  | 2 Bytes (0x0001=Rd/Wr, 0x0002=Burst)
     *					+-----------+
     *					| ACCESS    | 2 Bytes
     *					| CODE      |
     *					+-----------+
     *
     *					// COMMAND = 0x0001 (Rd/Wr)
     *					+-----------+
     *					| ACCESS    | 4 Bytes (OP Code [001=READ, 010=WRITE, etc.], Byte Enable [EEEE])
     *					| COMMAND   |
     *					+-----------+
     *					| DATA      | 4 Bytes (AAAA..AAAA[23:0] Register Address)
     *					+-----------+
     *
     *					// COMMAND = 0x0002 (Burst)
     *					+-----------+
     *					| ACCESS    | 4 Bytes (2 bits Direction [01=READ, 10=WRITE])
     *					| COMMAND/DATA|
     *					+-----------+
     *					| DATA      | 4 Bytes (AAAA..AAAA[23:0] Starting Register Address)
     *					+-----------+
     *
     *					// COMMAND = 0x0001 (WAIT/MODIFY)
     *					+-----------+
     *					| ACCESS    | 4 Bytes (0xmaskmask [Mask (1) bit in reg. to be tested/set])
     *					| COMMAND/DATA|
     *					+-----------+
     *					| DATA      | 4 Bytes (dddddddd data written/read)
     *					+-----------+
     *
     *					// COMMAND = 0x0002 (Burst)
     *					+-----------+
     *					| ACCESS    | 4 Bytes (25 0's and 6 bits of burst count)
     *					| COMMAND/DATA|
     *					+-----------+
     *
     *					+-----------+
     *					| PAD       | Variable
     *					+-----------+
     *					| FRAME     | 4 Bytes
     *					| CHECK SEQUENCE|
     *					+-----------+
     *					| EXTENSION | Variable
     *					+-----------+
     *
     *					Bits Transmitted from Left to Right
     *
     */
}