void __4_14_3__REDUCED_GIGABIT_MEDIA_INDEPENDENT_INTERFACE_RGMII_PORT_6() {
    /**
     * @group:       	4.14.3 REDUCED GIGABIT MEDIA INDEPENDENT INTERFACE (RGMII) (PORT 6)
     *
     * @description:	RGMII provides a common interface between RGMII PHYs and MACs, and has the following key characteristics:
     *					• Pin count is reduced from 24 pins for GMII to 12 pins for RGMII.
     *					• All speeds (10Mbps, 100Mbps and 1000Mbps) are supported at both half- and full-duplex.
     *					• Data transmission and reception are independent and belong to separate signal groups.
     *					• Transmit data and receive data are each four bits wide - a nibble.
     *					In RGMII operation, the RGMII pins function as follows:
     *					• The MAC sources the transmit reference clock, TX_CLK6, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and
     *					2.5MHz for 10Mbps.
     *					• The PHY recovers and sources the receive reference clock, RX_CLK6, at 125MHz for 1000Mbps, 25MHz for
     *					100Mbps, and 2.5MHz for 10Mbps.
     *					• For 1000BASE-T, the transmit data, TXD6_[3:0], is presented on both edges of TX_CLK6, and the received data,
     *					RXD6_[3:0], is clocked out on both edges of the recovered 125MHz clock, RX_CLK6.
     *					• For 10BASE-T/100BASE-TX, the MAC holds TX_CTL6 low until both the PHY and MAC operate at the same
     *					speed. During the speed transition, the receive clock is stretched on either a positive of negative pulse to ensure
     *					that no clock glitch is presented to the MAC.
     *					• TX_ER6 and RX_ER6 are combined with TX_EN6 and RX_DV6, respectively, to form TX_CTL6 and RX_CTL6.
     *					These two RGMII control signals are valid at the falling clock edge.
     *					After power-up or reset, the device is configured to RGMII mode if the appropriate configuration strap pins are set to
     *					one of the RGMII mode capability options. Refer to Section 3.2.1, "Configuration Straps," on page 18 for available
     *					options. Note that there is no mechanism for the RGMII interface to adapt its speed automatically to the speed of the
     *					connected RGMII device. A configuration strap option sets the speed of the RGMII interface at power-up to either
     *					1000Mbps or 100Mbps. A control register can override the configuration strap option and set the RGMII speed to either
     *					1000, 100 or 10Mbps. If a PHY is connected to the RGMII port, it should be ensured that the PHY link speed is fixed in
     *					order to avoid a mismatch to the RGMII speed.
     *					The device provides the option to add a minimum of 1.5ns internal delay to either TX_CLK6 or RX_CLK6, via the RGMII
     *					Internal Delay control bits in the XMII Port Control 1 Register. This can reduce or eliminate the need to add trace delay
     *					to the clock signals on the printed circuit board. RGMII_ID_ig enables delay on TX_CLK6, and the default is off.
     *					RGMII_ID_eg enables delay on RX_CLK6, and the default is on. Users should also be aware of any internal clock delay
     *					that may be added by the connected RGMII device.
     *
     *
     *					TABLE 4-34: RGMII SIGNAL DESCRIPTIONS
     *					+-----------+------------+-------------------+-------------------+------------------------------------------+
     *					| RGMII Signal| RGMII Signal| Pin Direction     | Pin Direction     | RGMII Signal Description                 |
     *					| Name (per | (per       | (with respect to  | (with respect to  |                                          |
     *					| spec)     | KSZ9477S)  | PHY, KSZ9477S)    | MAC)              |                                          |
     *					+-----------+------------+-------------------+-------------------+------------------------------------------+
     *					| TXC       | TX_CLK6    | Input             | Output            | Transmit Reference Clock (125MHz for     |
     *					|           |            |                   |                   | 1000Mbps, 25MHz for 100Mbps, 2.5MHz for |
     *					|           |            |                   |                   | 10Mbps)                                  |
     *					+-----------+------------+-------------------+-------------------+------------------------------------------+
     *					| TX_CTL    | TX_CTL6    | Input             | Output            | Transmit Control                         |
     *					+-----------+------------+-------------------+-------------------+------------------------------------------+
     *					| TXD[3:0]  | TXD6_[3:0] | Input             | Output            | Transmit Data [3:0]                      |
     *					+-----------+------------+-------------------+-------------------+------------------------------------------+
     *					| RXC       | RX_CLK6    | Output            | Input             | Receive Reference Clock (125MHz for     |
     *					|           |            |                   |                   | 1000Mbps, 25MHz for 100Mbps, 2.5MHz for |
     *					|           |            |                   |                   | 10Mbps)                                  |
     *					+-----------+------------+-------------------+-------------------+------------------------------------------+
     *					| RX_CTL    | RX_CTL6    | Output            | Input             | Receive Control                          |
     *					+-----------+------------+-------------------+-------------------+------------------------------------------+
     *					| RXD[3:0]  | RXD6_[3:0] | Output            | Input             | Receive Data [3:0]                       |
     *					+-----------+------------+-------------------+-------------------+------------------------------------------+
     *
     */
}