void __4_1_1_4__TIMING_RECOVERY_CIRCUIT() {
    /**
     * @group:       	4.1.1.4 Timing Recovery Circuit
     *
     * @description: 	In 1000BASE-T mode, the mixed signal clock recovery circuit, together with the digital phase locked loop (PLL), is used
     * 					to recover and track the incoming timing information from the received data. The digital PLL has very low long-term jitter
     * 					to maximize the signal-to-noise ratio of the receive signal.
     * 					The 1000BASE-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to
     * 					the 1000BASE-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This
     * 					also helps to facilitate echo cancellation and NEXT removal.
     */
}