void __4_8__NAND_Tree_Support() {
    /**
     * @group:       	4.8 NAND Tree Support
     *
     * @description:	The KSZ9477S provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND tree
     *					is a chain of nested NAND gates in which each KSZ9477S digital I/O (NAND tree input) pin is an input to one NAND
     *					gate along the chain. At the end of the chain, the INTRP_N pin provides the output for the last NAND gate.
     *					The NAND tree test process includes:
     *					• Enabling NAND tree mode
     *					• Pulling all NAND tree input pins high
     *					• Driving low each NAND tree input pin sequentially per the NAND tree pin order, starting with the first row of
     *					Table 4-24.
     *					• Checking the NAND tree output to ensure there is a toggle high-to-low or low-to-high for each NAND tree input
     *					driven low.
     *
     *					TABLE 4-24: NAND TREE TEST PIN ORDER
     *					+------------------+------------+-----------+-----------------------+
     *					| NAND Tree        | Pin Number | Pin Name  | NAND Tree Description |
     *					| Sequence         |            |           |                       |
     *					+------------------+------------+-----------+-----------------------+
     *					| 1                | 85         | LED4_0    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 2                | 86         | LED4_1    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 3                | 88         | LED3_0    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 4                | 89         | LED3_1    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 5                | 90         | GPIO_1    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 6                | 91         | LED2_0    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 7                | 92         | LED2_1    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 8                | 93         | PME_N     | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 9                | 95         | SYNCLKO   | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 10               | 97         | SDO       | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 11               | 98         | SDI/SDA/MDIO| Input               |
     *					+------------------+------------+-----------+-----------------------+
     *					| 12               | 100        | SCS_N     | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 13               | 101        | SCL/MDC   | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 14               | 102        | LED5_0    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 15               | 103        | LED5_1    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 16               | 105        | LED1_0    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 17               | 106        | LED1_1    | Input                 |
     *					+------------------+------------+-----------+-----------------------+
     *					| 18               | 94         | INTRP_N   | Output                |
     *					+------------------+------------+-----------+-----------------------+
     *
     *					The following procedure can be used to check for faults on the KSZ9477S digital I/O pin connections to the board:
     *					1. Enable NAND tree mode via the LED2_1, LED2_0, and LED4_0 configuration strap pins option.
     *					2. Use board logic to drive all KSZ9477S NAND tree input pins high and verify that the INTRP_N pin output is high.
     *					3. Use board logic to drive each NAND tree input pin, per the NAND Tree pin order, as follows:
     *					a) Toggle the first pin in the NAND tree sequence (LED4_0) from high to low, and verify the INTRP_N pin
     *					switches from high to low to indicate that the first pin is connected properly.
     *					b) Leave the first pin (LED4_0) low.
     *					c) Toggle the second pin in the NAND tree sequence (LED4_1) from high to low, and verify the INTRP_N pin
     *					switches from low to high to indicate that the second pin is connected properly.
     *					d) Leave the first pin (LED4_0) and the second pin (LED4_1) low.
     *					e) Toggle the third pin in the NAND tree sequence (LED3_0) from high to low, and verify the INTRP_N pin
     *					switches from high to low to indicate that the third pin is connected properly.
     *					f) Continue with this sequence until all KSZ9477S NAND tree input pins have been toggled.
     *					Each KSZ9477S NAND tree input pin must cause the INTRP_N output pin to toggle high-to-low or low-to-high to indi-
     *					cate a good connection. If the INTRP_N pin fails to toggle when the KSZ9477S input pin toggles from high to low, the
     *					input pin has a fault.
     *
     *
     */
}