void __4_9_1__PRIMARY_CLOCK() {
    /**
     * @group:       	4.9.1 PRIMARY CLOCK
     *
     * @description:	4.9.1 PRIMARY CLOCK
     *					The device requires a 25MHz reference clock input at the XI pin. This clock is internally multiplied up and used to clock
     *					all of the internal logic and switching functions. It is also normally used as to clock the PHY transmit paths. This clock
     *					may be supplied by connecting a crystal between the XI and XO pins (and appropriate load capacitors to ground). Alter-
     *					natively, an external CMOS clock signal may drive XI, while XO is left unconnected. The XI/XO block is powered from
     *					AVDDH.
     *
     *
     *
     */
}