void __4_9_2__PORT_6_RGMII_MII_RMII_CLOCKS() {
    /**
     * @group:       	4.9.2 PORT 6 RGMII/MII/RMII CLOCKS
     *
     * @description:	The MII interface is clocked asymmetrically, with the PHY device driving both the RX_CLK6 receive clock and the TX_-
     *					CLK6 transmit clock to the MAC device. The MII port may be configured at reset by a strapping option to take the role
     *					of either the PHY or the MAC. RX_CLK6 and TX_CLK6 are therefore either both inputs or both outputs, depending on
     *					the MII mode.
     *					The RMII interface uses a single 50MHz clock. This REFCLK may be sourced either from the KSZ9477S or from the
     *					connected device. A strapping option is used to select the mode. “Normal Mode” is the mode where the other device
     *					supplies the clock, and the clock is an input to the REFCLKI6 pin of the device. “Clock Mode” is the mode where the
     *					KSZ9477S generates the 50MHz clock on the REFCLKO6 pin.
     *					The RGMII interface employs source synchronous clocking, so it is symmetrical and does not require a mode selection.
     *					An output clock is generated on the RX_CLK6 pin, while an input clock is received on the TX_CLK6 pin. The clock
     *					speed scales with the interface data rate - either 10, 100 or 1000 Mbps. A strapping option is used to select between
     *					the 100 and 1000 Mbps speeds. If the 10 Mbps rate is required, then a register setting is used to set that speed.
     *					The Port 6 MAC interface is powered from VDDIO.

     * @note:			Refer to Section 3.2.1, "Configuration Straps," on page 18 for additional information on using configuration
     * 					straps.
     *
     */
}