void __4_9_5__SYNCHRONOUS_ETHERNET_AND_SYNCLKO() {
    /**
     * @group:       		4.9.5 SYNCHRONOUS ETHERNET AND SYNCLKO
     *
     * @description:		An output clock is provided on the SYNCLKO pin. By default it is derived from the 25MHz input reference clock on XI,
     *						but the source can be selected to be the recovered clock from any of the PHY ports. This recovered clock may then feed
     *						an external device with a low bandwidth PLL and hold-over feature for use in Synchronous Ethernet applications. A
     *						25MHz clock derived from SYNCLKO may then be used as the input to XI.
     *						The output frequency choices are 25MHz (default) and 125MHz. If not needed, this output clock can also be disabled.
     *						SYNCLKO is controlled via the Output Clock Control Register, and is powered from VDDIO.
     *
     * @note:				In order to utilize synchronous Ethernet functions, additional hardware design rules must be taken into con-
     *						sideration. Contact your local Microchip sales representative for additional information.
     *
     */
}