void __5_0__DEVICE_REGISTERS() { /** * @group: 5.0 DEVICE REGISTERS * * @description: The KSZ9477S has a rich set of registers for device management. The registers are accessed by the SPI or I2C inter- * faces, or by in-band management. Alternatively, the MIIM interface can be used to access the PHY registers only. The * MIIM interface cannot access the switch registers. * A 16-bit address is used to access the device registers. This address is split into three hierarchical spaces, as shown * in Figure 5-1. These three spaces are used to designate the port/channel (4-bits), function (page) of the port (4-bits), * and register of function (8-bits). The individual ports are numbered 1 through 7. In the port space, a value of 0 is used * for global registers. Address bit 15 is always 0 * * FIGURE 5-1: REGISTER ADDRESS MAPPING * +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ * * Examples: * 0 N N N 0 1 0 0 0 0 0 0 1 0 0 0 = 0xN408 * 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 = 0x0312 * * REGISTER ADDRESS MAPPING * +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | * +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ * | <--- Port Space --> |<- Function Space (Page)-> | <------ Register Space ------> | * +-------------+-------------+---------------------------+-----------------------+-------------------------------+ * ^ ^ ^ * | | | * +---------+ +---------+ +-----------+ * | N=Port # (1-7) | | Function Codes | | Control, Status, Etc. | * | 0=Global | | (z.B. 0=Op, 2=PHY) | +-------------------------+ * +-----------------+ +-------------------------+ * | * +---------v-----------+ * | Port Functions | * | (z.B. 4=MAC, 6=ACL) | * +---------------------+ * * +--------------------------------------------+------+------------------------------------------+ * | Kontext | Code | Beschreibung | * +--------------------------------------------+------+------------------------------------------+ * | | | | * | +------+------------------------------------------+ * | | 1 | I/O Interface | * | +------+------------------------------------------+ * | | 2 | PHY | * | +------+------------------------------------------+ * | | 3 | General | * | +------+------------------------------------------+ * | 0 = Global | 4 | Look-up Tables, HSR | * | +------+------------------------------------------+ * | | 5 | IEEE 1588 PTP | * | +------+------------------------------------------+ * | | 6 | Ring Redundancy | * | +------+------------------------------------------+ * | | 7-F | Reserved | * +--------------------------------------------+------+------------------------------------------+ * | | 0 | Operation | * | +------+------------------------------------------+ * | | 1 | PHY | * | +------+------------------------------------------+ * | | 2 | SGMII | * | +------+------------------------------------------+ * | | 3 | RGMII / MII / RMII | * | +------+------------------------------------------+ * | | 4 | MAC | * | +------+------------------------------------------+ * | | 5 | MIB Counters | * | N = Port # (Values are 1-7) +------+------------------------------------------+ * | | 6 | ACL | * | +------+------------------------------------------+ * | | 7 | Reserved | * | +------+------------------------------------------+ * | | 8 | Ingress – Classification, Policing | * | +------+------------------------------------------+ * | | 9 | Egress – Shaping | * | +------+------------------------------------------+ * | | A | Queue management | * | +------+------------------------------------------+ * | | B | Address lookup engine | * | +------+------------------------------------------+ * | | C | IEEE 1588 PTP | * | +------+------------------------------------------+ * | | D-F | Reserved | * +--------------------------------------------+------+------------------------------------------+ * * * Register addressing is by bytes, and the management interface (SPI, I 2 C or in-band) transfers data by bytes. Where * registers are shown as 16-bits or 32-bits, this is for descriptive purposes only. Data can always be written and read as * individual bytes and in any order. * For multi-byte registers, the data is addressed in a big-endian format, with the most significant byte at the lowest * address, and the least significant byte at the highest address, as shown in Figure 5-2. * * =========================================== * FIGURE 5-2: BYTE ORDERING * =========================================== * * 16-Bit Register: * ---------------- * Das 16-Bit-Register mit dem Wert 0A0B0 wird in zwei Bytes in den Speicher geschrieben: * * Adresse 'a': Enthält das höherwertige Byte (MSB) 0A. * * Adresse 'a+1': Enthält das niederwertige Byte (LSB) 0B. * * 32-Bit Register: * ---------------- * Das 32-Bit-Register mit dem Wert 0A0B0C0D wird in vier Bytes in den Speicher geschrieben: * * Adresse 'a': Enthält das erste Byte 0A. * * Adresse 'a+1': Enthält das zweite Byte 0B. * * Adresse 'a+2': Enthält das dritte Byte 0C. * * Adresse 'a+3': Enthält das vierte Byte 0D. * * Hinweis: Dies illustriert die Big-Endian-Byte-Reihenfolge. * ---------------- * * * The global and port register address maps are detailed in Table 5-1 and Table 5-2, respectively. Table 1-3, “Register * Nomenclature,” on page 7 provides a list of register bit type notations. * The remainder of this chapter is organized as follows: * • Global Registers * • Port Registers * • Tables and MIB Counters (Access) * • MDIO Manageable Device (MMD) Registers (Indirect) * • SGMII Registers (Indirect) * * * TABLE 5-1: GLOBAL REGISTER ADDRESS MAP * +-----------------+------------------------------------------------------+ * | Address | Functional Group | * +-----------------+------------------------------------------------------+ * | 0x0000 - 0x00FF | Global Operation Control Registers | * +-----------------+------------------------------------------------------+ * | 0x0100 - 0x01FF | Global I/O Control Registers | * +-----------------+------------------------------------------------------+ * | 0x0200 - 0x02FF | Global PHY Control and Status Registers | * +-----------------+------------------------------------------------------+ * | 0x0300 - 0x03FF | Global Switch Control Registers | * +-----------------+------------------------------------------------------+ * | 0x0400 - 0x04FF | Global Switch Look Up Engine (LUE) Control Registers | * +-----------------+------------------------------------------------------+ * | 0x0500 - 0x05FF | Global Switch PTP Control Registers | * +-----------------+------------------------------------------------------+ * | 0x0600 - 0x06FF | Global Switch Ring Redundancy Control Registers | * +-----------------+------------------------------------------------------+ * | 0x0700 - 0x0FFF | RESERVED | * +-----------------+------------------------------------------------------+ * * * TABLE 5-2: PORT N (1-7) REGISTER ADDRESS MAP * +-----------------+----------------------------------------------------+ * | Address | Functional Group | * +-----------------+----------------------------------------------------+ * | 0xN000 - 0xN0FF | Port N: Port Operation Control Registers | * +-----------------+----------------------------------------------------+ * | 0xN100 - 0xN1FF | Port N: Port Ethernet PHY Registers | * +-----------------+----------------------------------------------------+ * | 0xN200 - 0xN2FF | Port N: Port SGMII Control Registers | * +-----------------+----------------------------------------------------+ * | 0xN300 - 0xN3FF | Port N: Port RGMII/MII/RMII Control Registers | * +-----------------+----------------------------------------------------+ * | 0xN400 - 0xN4FF | Port N: Port Switch MAC Control Registers | * +-----------------+----------------------------------------------------+ * | 0xN500 - 0xN5FF | Port N: Port Switch MIB Counters Registers | * +-----------------+----------------------------------------------------+ * | 0xN600 - 0xN6FF | Port N: Port Switch ACL Control Registers | * +-----------------+----------------------------------------------------+ * | 0xN700 - 0xN7FF | RESERVED | * +-----------------+----------------------------------------------------+ * | 0xN800 - 0xN8FF | Port N: Port Switch Ingress Control Registers | * +-----------------+----------------------------------------------------+ * | 0xN900 - 0xN9FF | Port N: Port Switch Egress Control Registers | * +-----------------+----------------------------------------------------+ * | 0xNA00 - 0xNAFF | Port N: Port Switch Queue Management Control R. | * +-----------------+----------------------------------------------------+ * | 0xNB00 - 0xNBFF | Port N: Port Switch Address Lookup Control R. | * +-----------------+----------------------------------------------------+ * | 0xNC00 - 0xNCFF | Port N: Port Switch PTP Control Registers | * +-----------------+----------------------------------------------------+ * * * @note: RESERVED address space must not be written under any circumstances. Failure to heed this warn- * ing may result in untoward operation and unexpected results. If it is necessary to write to registers * which contain both writable and reserved bits in the same register, the user should first read back * the reserved bits (RO or R/W), “OR” the desired settable bits with the value read, and then write * back the “ORed” value to the register. * */ }