void __5_1_2_1__0x0100_0x0100_08_Serial_IO_Control_Register() {
/**
 * @header:     	5.1.2.1 Serial I/O Control Register
 * @address:    	0x0100 | Size: 8 bits
 *
 * @description:
 *
 * @note:
 *
 * +------+-----------------------------------------------------------------------+------+---------+
 * | Bits | Description                                                           | Type | Default |
 * +------+-----------------------------------------------------------------------+------+---------+
 * | 7:3  | RESERVED                                                              | R/W  | 0100_0b |
 * +------+-----------------------------------------------------------------------+------+---------+
 * | 2    | MIIM Preamble Suppression                                             | R/W  | 0b      |
 * |      | This feature affects only the MIIM (MDIO / MDC) interface. When using  |      |         |
 * |      | SPI or I2C, this bit has no effect.                                   |      |         |
 * |      | 0 = Normal operation. The switch always expects the MIIM preamble.    |      |         |
 * |      | 1 = The switch will respond to MIIM commands even in the absence of a |      |         |
 * |      | preamble.                                                             |      |         |
 * +------+-----------------------------------------------------------------------+------+---------+
 * | 1    | Automatic SPI Data Out Edge Select                                    | R/W  | 1b      |
 * |      | When enabled, this feature automatically determines the edge of SCL   |      |         |
 * |      | that is used to clock out the SPI data on SDO. If SCL >= ~25MHz, SDO  |      |         |
 * |      | data is clocked by the rising edge of SCL. If SCL < ~25 MHz, SDO data |      |         |
 * |      | is clocked by the falling edge of SCL.                                |      |         |
 * |      | 0 = The automatic feature is disabled, and bit 0 determines the SCL   |      |         |
 * |      | clock edge used for SDO.                                              |      |         |
 * |      | 1 = The automatic feature is enabled, and bit 0 is ignored.           |      |         |
 * +------+-----------------------------------------------------------------------+------+---------+
 * | 0    | SPI Data Out Edge Select                                              | R/W  | 0b      |
 * |      | When bit 1 is zero, then this bit determines the clock edge used for  |      |         |
 * |      | SPI data out. When bit 1 is set to 1, this bit is ignored.            |      |         |
 * |      | 0 = SDO data is clocked by the falling edge of SCL                    |      |         |
 * |      | 1 = SDO data is clocked by the rising edge of SCL                     |      |         |
 * +------+-----------------------------------------------------------------------+------+---------+

 *
 */
}