void __5_1_4_30__0x0336_0x0336_08_Switch_MIB_Control_Register() {
/**
 * @header:     	5.1.4.30 Switch MIB Control Register
 * @address:    	0x0336 | Size: 8 bits
 *
 * @description:	MIB counters are provided on a per-port basis. They are read and controlled via the Port N: Port Switch MIB Counters
 *					Registers (0xN500 - 0xN5FF).
 *
 * @note:
 *
 * +------+-----------------------------------------------------------------------+------+---------+
 * | Bits | Description                                                           | Type | Default |
 * +------+-----------------------------------------------------------------------+------+---------+
 * | 7    | Flush MIB Counters                                                    | R/W  | 0b      |
 * |      | 1 = Flush all MIB counters of enabled ports. Refer to the Port MIB    | SC   |         |
 * |      |     Control and Status Register.                                      |      |         |
 * |      | 0 = Normal counter operation                                          |      |         |
 * +------+-----------------------------------------------------------------------+------+---------+
 * | 6    | Freeze MIB Counters                                                   | R/W  | 0b      |
 * |      | 1 = Freeze MIB counters of enabled ports. Refer to the Port MIB       |      |         |
 * |      |     Control and Status Register.                                      |      |         |
 * |      | 0 = Normal counter operation                                          |      |         |
 * +------+-----------------------------------------------------------------------+------+---------+
 * | 5:0  | RESERVED                                                              | RO   | 00_0000b|
 * +------+-----------------------------------------------------------------------+------+---------+
 *
 */
}