void __5_2_1_8__0xN030_0xN030_08_Port_Status_Register() {
/**
 * @header:     	5.2.1.8 Port Status Register
 * @address:    	0xN030 - 0xN030 | Size: 8 bits
 * @port:			Port N: 1-7
 *
 * @description:
 *
 * @note:
 *
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | Bits  | Description                                                                        | Type   | Default    |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 7:5   | RESERVED                                                                           | RO     | 000        |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 4:3   | Port Speed Status                                                                  | RO     | -          |
 * |       | For non-PHY ports, these bits duplicate the speed setting in the XMII Port         |        |            |
 * |       | Control 1 Register bit 6 and XMII Port Control 0 Register bit 4.                   |        |            |
 * |       | For PHY ports, these bits indicate the actual link speed, which is also            |        |            |
 * |       | available in the PHY Control Register.                                             |        |            |
 * |       | 00 = 10 Mb/s                                                                       |        |            |
 * |       | 01 = 100 Mb/s                                                                      |        |            |
 * |       | 10 = 1000 Mb/s                                                                     |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 2     | Port Duplex Status                                                                 | RO     | 1          |
 * |       | For non-PHY ports, this bit duplicates the duplex setting in the XMII Port         |        |            |
 * |       | Control 0 Register bit 6.                                                          |        |            |
 * |       | For PHY ports, this bit indicates the actual link duplex, which is also available  |        |            |
 * |       | in the PHY Control Register.                                                       |        |            |
 * |       | 1 = Fu                                                                             |        |            |
 * |       | 0 = Half duplex                                                                    |        |            |
 * |       | RO 1 or -                                                                          |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 1     | Transmit Flow Control Enabled Status                                               | RO     | -          |
 * |       | For non-PHY ports, this bit duplicates the Tx FC enable bit 5 in the XMII Port     |        |            |
 * |       | Control 0 Register.                                                                |        |            |
 * |       | For PHY ports, this bit is set only when FC is enabled (PHY Auto-Negotiation       |        |            |
 * |       | Advertisement Register, bits 11:10), link is up and FC is established via auto-    |        |            |
 * |       | negotiation.                                                                       |        |            |
 * |       | 1 = TX flow control is enabled                                                     |        |            |
 * |       | 0 = Disabled                                                                       |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 0     | Receive Flow Control Enabled Status                                                | RO     | -          |
 * |       | For non-PHY ports, this bit duplicates the Rx FC enable bit 3 in the XMII Port     |        |            |
 * |       | Control 0 Register.                                                                |        |            |
 * |       | For PHY ports, this bit is set only when FC is enabled (PHY Auto-Negotiation       |        |            |
 * |       | Advertisement Register, bits 11:10), link is up and FC is established via auto-    |        |            |
 * |       | negotiation.                                                                       |        |            |
 * |       | 1 = RX flow control is enabled                                                     |        |            |
 * |       | 0 = Disabled                                                                       |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 *
 */
}