void __5_2_2_1__0xN100_0xN101_16_PHY_Basic_Control_Register() {
/**
 * @header:     	5.2.2.1 PHY Basic Control Register
 * @address:    	0xN100 - 0xN101 | Size: 16 bits
 * @port:			Port N: 1-5
 * @phy_register:	0x00
 *
 * @description:
 *
 * @note:			Note 5-4 The default value of this field is determined by the associated configuration strap value. Refer to
 *					Section 3.2.1, "Configuration Straps," on page 18 for additional information.
 *
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | Bits  | Description                                                                        | Type   | Default    |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 15    | PHY Software Reset                                                                 | R/W/SC | 0b         |
 * |       | Set this bit to reset this PHY. Registers are not reset. This bit is self-         |        |            |
 * |       | clearing.                                                                          |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 14    | Local Loopback Mode                                                                | R/W    | 0b         |
 * |       | Data going from the internal switch fabric to an egress port is looped back at     |        |            |
 * |       | that egress port and returned to the internal switch fabric.                       |        |            |
 * |       | 1 = Local Loopback mode                                                            |        |            |
 * |       | 0 = Normal operation                                                               |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 13    | Speed Select (LSB)                                                                 | R/W    | Note 5-4   |
 * |       | This bit is ignored if auto-negotiation is enabled (bit 12 in this register).      |        |            |
 * |       | Bits [6, 13]                                                                       |        |            |
 * |       | 11 = Reserved                                                                      |        |            |
 * |       | 10 = 1000 Mb/s                                                                     |        |            |
 * |       | 01 = 100 Mb/s                                                                      |        |            |
 * |       | 00 = 10 Mb/s                                                                       |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 12    | Auto-Negotiation Enable                                                            | R/W    | Note 5-4   |
 * |       | 1 = Auto-negotiation is enabled                                                    |        |            |
 * |       | 0 = Auto-negotiation is disabled                                                   |        |            |
 * |       | The initial value of this bit is determined by a strapping option, but it may be   |        |            |
 * |       | overwritten.                                                                       |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 11    | Power Down                                                                         | R/W    | 0b         |
 * |       | 1 = Power-down mode                                                                |        |            |
 * |       | 0 = Normal operation                                                               |        |            |
 * |       | When this bit is set to ‘1’, the link-down status might not get updated in the     |        |            |
 * |       | PHY status register. Software should note link is down and should not rely on      |        |            |
 * |       | the PHY status register link status.                                               |        |            |
 * |       | After this bit is changed from ‘1’ to ‘0’, an internal reset is performed. Wait a  |        |            |
 * |       | minimum of 1ms before read/write access to this PHY’s registers.                   |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 10    | Isolate                                                                            | R/W    | 0b         |
 * |       | 1 = Logical isolation of the PHY from the switch core                              |        |            |
 * |       | 0 = Normal operation                                                               |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 9     | Re-start Auto-Negotiation                                                          | SC     | 0b         |
 * |       | Set this bit to re-start auto-negotiation. This bit is self-clearing.              |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 8     | Duplex Mode                                                                        | R/W    | 1b         |
 * |       | This bit is ignored if auto-negotiation is enabled (bit 12 in this register).      |        |            |
 * |       | 1 = Fu                                                                             |        |            |
 * |       | 0 = Half duplex                                                                    |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 7     | Collision Test                                                                     | R/W    | 0b         |
 * |       | 1 = Enable COL test                                                                |        |            |
 * |       | 0 = Disable COL test                                                               |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 6     | Speed Select (MSB)                                                                 | R/W    | Note 5-4   |
 * |       | This bit is ignored if auto-negotiation is enabled (bit 12 in this register).      |        |            |
 * |       | Bits [6, 13]                                                                       |        |            |
 * |       | 11 = Reserved                                                                      |        |            |
 * |       | 10 = 1000 Mb/s                                                                     |        |            |
 * |       | 01 = 100 Mb/s                                                                      |        |            |
 * |       | 00 = 10 Mb/s                                                                       |        |            |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 * | 5:0   | RESERVED                                                                           | RO     | 0x00       |
 * +-------+------------------------------------------------------------------------------------+--------+------------+
 *
 */
}