void __5_2_3__PORT_N_PORT_SGMII_CONTROL_REGISTERS() {
/**
 * @header:     	5.2.3 PORT N: PORT SGMII CONTROL REGISTERS (0xN200 - 0xN2FF)
 * @address:
 * @port:
 * @phy_register:
 *
 * @description:	The Port 7 SGMII registers are accessed indirectly using the following two registers. The indirect SGMII registers, along
 *					with details on how to access them, are described in Section 5.5, "SGMII Registers (Indirect)," on page 228.
 *					Steps for SGMII register reads:
 *					1. Write the SGMII register address to the Port SGMII Address Register.
 *					2. Read the SGMII register data from the Port SGMII Data Register.
 *					Steps for SGMII register write:
 *					1. Write the SGMII register address to the Port SGMII Address Register.
 *					2. Write the SGMII register data to the Port SGMII Data Register.
 *
 * @note:			The Port SGMII Address Register must be written as one continuous 32-bit write, and the Port SGMII Data
 *					Register must be written as one continuous 16-bit write. These registers may not function correctly if written
 *					as multiple 8-bit writes.
 *
 *
 */
}