void __5_3_5__ACCESS_CONTROL_LIST_ACL_TABLE() {
    /**
 * @header:     	5.3.5 ACCESS CONTROL LIST (ACL) TABLE
 * @address:
 * @port:
 * @phy_register:
 *
 * @description:	ACL filtering is implemented individually per-port. The ACL tables are accessed using the Port N: Port Switch ACL Con-
 *					trol Registers (0xN600 - 0xN6FF). The 16 entries in each ACL table are addressed indirectly by an index register.
 *					Table 5-5 shows how the various fields of the ACL Table entries are mapped to data registers. The Port ACL Byte Enable
 *					MSB Register and Port ACL Byte Enable LSB Register make it possible to write or read any combination of bytes. This
 *					is useful for writing the Matching rule, Action rule and Process field separately. There are 16 bits in these byte enable
 *					registers, corresponding to the 16 data registers Port ACL Access 0 Register through Port ACL Access F Register. Note
 *					that the enable bits are applied in reverse order:
 *					Bit 0 for the Port ACL Access F Register
 *					Bit 1 for the Port ACL Access E Register
 *					…
 *					Bit 14 for the Port ACL Access 1 Register
 *					Bit 15 for the Port ACL Access 0 Register
 *					Also note that the Port ACL Access C Register is not used, so byte enable bit 3 is a don't care.
 *
 * @note:
 *
 *
 *
 * @table:			TABLE 5-5: ACL FIELD REGISTER MAPPING
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| Register| Bits |     MD = 01      |  Count Mode      |     MD = 10      |     MD = 11      |
 *					|         |      |     ENB = 00     |  MD=01, ENB!=00  |                  |                  |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN600  | 7:4  | RESERVED         | RESERVED         | RESERVED         | RESERVED         |
 *					|         | 3:0  | FRN [3:0]        | FRN [3:0]        | FRN [3:0]        | FRN [3:0]        |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN601  | 7:6  | RESERVED         | RESERVED         | RESERVED         | RESERVED         |
 *					|         | 5:4  | MD [1:0]         | MD [1:0]         | MD [1:0]         | MD [1:0]         |
 *					|         | 3:2  | ENB [1:0]        | ENB [1:0]        | ENB [1:0]        | ENB [1:0]        |
 *					|         |  1   | S / D            | S / D            | S / D            | S / D            |
 *					|         |  0   | EQ               | EQ               | EQ               | EQ               |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN602  | 7:0  | MAC ADDR [47:0]  | IP ADDR [31:0]   | MAX PORT [15:0]  | MAX PORT [15:0]  |
 *					| 0xN603  | 7:0  |                  |                  |                  |                  |
 *					| 0xN604  | 7:0  |                  |                  | MIN PORT [15:0]  | MIN PORT [15:0]  |
 *					| 0xN605  | 7:0  |                  |                  |                  |                  |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN606  | 7:3  | MAC ADDR [47:0]  | IP MASK [31:0]   | RESERVED         | RESERVED         |
 *					|         | 2:1  | (cont.)          |                  | PC [1:0]         | PC [1:0]         |
 *					|         |  0   |                  |                  | PRO [7:0]        | PRO [7:0]        |
 *					| 0xN607  | 7:1  |                  |                  | (cont.)          | (cont.)          |
 *					|         |  0   |                  |                  | FME              | FME              |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN608  | 7:0  | TYPE [15:0]      | IP MASK [31:0]   | FMSK [7:0]       | FMSK [7:0]       |
 *					| 0xN609  | 7:0  |                  | (cont.)          | FLAG [7:0]       | FLAG [7:0]       |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN60A  | 7:6  | COUNT [10:3]     | PM [1:0]         | PM [1:0]         | PM [1:0]         |
 *					|         | 5:3  |                  | P [2:0]          | P [2:0]          | P [2:0]          |
 *					|         |  2   |                  | RPE              | RPE              | RPE              |
 *					|         | 1:0  |                  | RP [2:1]         | RP [2:1]         | RP [2:1]         |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN60B  |  7   | COUNT [2:0]      | RP [0]           | RP [0]           | RP [0]           |
 *					|         | 6:5  |                  | MM [1:0]         | MM [1:0]         | MM [1:0]         |
 *					|         | 4:0  | RESERVED         | RESERVED         | RESERVED         | RESERVED         |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN60C  | 7:0  | RESERVED         | RESERVED         | RESERVED         | RESERVED         |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN60D  |  7   | RESERVED         | FORWARD [6:0]    | FORWARD [6:0]    | FORWARD [6:0]    |
 *					|         |  6   | TU               |                  |                  |                  |
 *					|         |  5   | CA               |                  |                  |                  |
 *					|         | 4:0  | RESERVED         |                  |                  |                  |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *					| 0xN60E  | 7:0  | RESERVED         | RULESET [15:8]   | RULESET [15:8]   | RULESET [15:8]   |
 *					| 0xN60F  | 7:0  | RESERVED         | RULESET [7:0]    | RULESET [7:0]    | RULESET [7:0]    |
 *					+---------+------+------------------+------------------+------------------+------------------+
 *
 */
}