Index of /reg_databook

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[TXT]__0_0__OVERVIEW.c2026-02-10 16:29 13K 
[TXT]__1_0__PREFACE.c2026-02-10 16:29 117  
[TXT]__1_1__Glossary_of_Terms.c2026-02-10 16:29 17K 
[TXT]__1_2__Buffer_Types.c2026-02-10 16:29 2.3K 
[TXT]__1_3__Register_Nomenclature.c2026-02-10 16:29 136  
[TXT]__1_4__References.c2026-02-10 16:29 114  
[TXT]__2_0__INTRODUCTION.c2026-02-10 16:26 127  
[TXT]__2_1__General_Description.c2026-02-10 16:26 4.9K 
[TXT]__3_0__PIN_DESCRIPTIONS_AND_CONFIGURATION.c2026-02-10 16:26 171  
[TXT]__3_1__Pin_Assignments.c2026-02-10 16:26 8.3K 
[TXT]__3_2_1__CONFIGURATION_STRAPS.c2026-02-10 16:26 14K 
[TXT]__3_2__Pin_Descriptions.c2026-02-10 16:26 37K 
[TXT]__4_0__FUNCTIONAL_DESCRIPTION.c2026-02-10 16:26 729  
[TXT]__4_1_1_1__ANALOG_ECHO_CANCELLATION_CIRCUIT.c2026-02-10 16:26 414  
[TXT]__4_1_1_2__AUTOMATIC_GAIN_CONTROL_AGC.c2026-02-10 16:26 387  
[TXT]__4_1_1_3__ANALOG_TO_DIGITAL_CONVERTER_ADC.c2026-02-10 16:26 395  
[TXT]__4_1_1_4__TIMING_RECOVERY_CIRCUIT.c2026-02-10 16:26 808  
[TXT]__4_1_1_5__ADAPTIVE_EQUALIZER.c2026-02-10 16:26 1.1K 
[TXT]__4_1_1_6__TRELLIS_ENCODER_AND_DECODER.c2026-02-10 16:26 564  
[TXT]__4_1_1__1000BASE_T_TRANSCEIVER.c2026-02-10 16:26 471  
[TXT]__4_1_2_1__100BASE_TX_TRANSMIT.c2026-02-10 16:26 1.0K 
[TXT]__4_1_2_2__100BASE_TX_RECEIVE.c2026-02-10 16:26 1.7K 
[TXT]__4_1_2_3__SCRAMBLER_DE_SCRAMBLER.c2026-02-10 16:26 644  
[TXT]__4_1_2__100BASE_TX_TRANSCEIVER.c2026-02-10 16:26 134  
[TXT]__4_1_3_1__10BASE_TE_TRANSMIT.c2026-02-10 16:26 581  
[TXT]__4_1_3_2__10BASE_TE_RECEIVE.c2026-02-10 16:26 842  
[TXT]__4_1_3__10BASE_TE_TRANSCEIVER.c2026-02-10 16:26 381  
[TXT]__4_1_4__AUTO_MDI_MDI_X.c2026-02-10 16:26 2.2K 
[TXT]__4_1_5__PAIR_SWAP_ALIGNMENT_AND_POLARITY_CHECK.c2026-02-10 16:26 812  
[TXT]__4_1_6__WAVE_SHAPING_SLEW_RATE_CONTROL_AND_PARTIAL_RESPONSE.c2026-02-10 16:26 752  
[TXT]__4_1_7__AUTO_NEGOTIATION.c2026-02-10 16:26 7.3K 
[TXT]__4_1_8__QUIET_WIRE_FILTERING.c2026-02-10 16:26 3.4K 
[TXT]__4_1_9__FAST_LINK_UP.c2026-02-10 16:26 1.7K 
[TXT]__4_1_10_1__Usage.c2026-02-10 16:26 2.9K 
[TXT]__4_1_10__LinkMD_CABLE_DIAGNOSTICS.c2026-02-10 16:26 928  
[TXT]__4_1_11__LinkMD_ENHANCED_DIAGNOSTICS_RECEIVE_SIGNAL_QUALITY_INDICATOR.c2026-02-10 16:26 2.0K 
[TXT]__4_1_12__REMOTE_PHY_LOOPBACK.c2026-02-10 16:27 3.7K 
[TXT]__4_1__PHYSICAL_LAYER_TRANSCEIVER_PHY.c2026-02-10 16:26 1.1K 
[TXT]__4_2_1__SINGLE_LED_MODE.c2026-02-10 16:27 1.1K 
[TXT]__4_2_2__TRI_COLOR_DUAL_LED_MODE.c2026-02-10 16:27 1.7K 
[TXT]__4_2__LEDs.c2026-02-10 16:27 670  
[TXT]__4_3_1__MAC_OPERATION.c2026-02-10 16:27 1.6K 
[TXT]__4_3_2__INTER_PACKET_GAP_IPG.c2026-02-10 16:27 459  
[TXT]__4_3_3__BACK_OFF_ALGORITHM.c2026-02-10 16:27 313  
[TXT]__4_3_4__LATE_COLLISION.c2026-02-10 16:27 243  
[TXT]__4_3_5__LEGAL_PACKET_SIZE.c2026-02-10 16:27 555  
[TXT]__4_3_6__FLOW_CONTROL.c2026-02-10 16:27 1.5K 
[TXT]__4_3_7__HALF_DUPLEX_BACK_PRESSURE.c2026-02-10 16:27 1.6K 
[TXT]__4_3_8__FLOW_CONTROL_AND_BACK_PRESSURE_REGISTERS.c2026-02-10 16:27 3.1K 
[TXT]__4_3_9__BROADCAST_STORM_PROTECTION.c2026-02-10 16:27 1.1K 
[TXT]__4_3_10__SELF_ADDRESS_FILTERING.c2026-02-10 16:27 518  
[TXT]__4_3__Media_Access_Controller_MAC.c2026-02-10 16:27 159  
[TXT]__4_4_1__SWITCHING_ENGINE.c2026-02-10 16:27 1.3K 
[TXT]__4_4_2_1__Address_Lookup_ALU_Table.c2026-02-10 16:27 3.4K 
[TXT]__4_4_2_2__Static_Address_Table.c2026-02-10 16:27 504  
[TXT]__4_4_2_3__Reserved_Multicast_Address_Table.c2026-02-10 16:27 4.2K 
[TXT]__4_4_2_4__Learning.c2026-02-10 16:27 1.0K 
[TXT]__4_4_2_5__Migration.c2026-02-10 16:27 658  
[TXT]__4_4_2_6__Aging.c2026-02-10 16:27 753  
[TXT]__4_4_2_7__Forwarding.c2026-02-10 16:27 3.7K 
[TXT]__4_4_2_8__Lookup_Engine_Registers.c2026-02-10 16:27 3.1K 
[TXT]__4_4_2__ADDRESS_LOOKUP.c2026-02-10 16:27 439  
[TXT]__4_4_3_1__Non_Tag_Port_Based_VLAN.c2026-02-10 16:27 793  
[TXT]__4_4_3_2_1__Tag_Insertion_and_Removal.c2026-02-10 16:27 708  
[TXT]__4_4_3_2_2__Double_Tagging.c2026-02-10 16:27 1.9K 
[TXT]__4_4_3_2__Tag_Based_VLAN.c2026-02-10 16:27 15K 
[TXT]__4_4_3_3__VLAN_Registers.c2026-02-10 16:27 3.8K 
[TXT]__4_4_3__IEEE_802_1Q_VLAN.c2026-02-10 16:27 549  
[TXT]__4_4_4_1__Port_Based_Priority.c2026-02-10 16:27 478  
[TXT]__4_4_4_2__IEEE_802_1p_Based_Priority.c2026-02-10 16:27 1.4K 
[TXT]__4_4_4_3__IEEE_802_1p_Priority_Field_Re_Mapping.c2026-02-10 16:27 585  
[TXT]__4_4_4_4__DiffServ_DSCP_Priority_IP.c2026-02-10 16:27 494  
[TXT]__4_4_4_5__ACL_Priority.c2026-02-10 16:27 329  
[TXT]__4_4_4__QUALITY_OF_SERVICE_QOS_PRIORITY_SUPPORT.c2026-02-10 16:27 1.3K 
[TXT]__4_4_5_1__Two_Rate_Three_Color_Marker.c2026-02-10 16:27 908  
[TXT]__4_4_5_2__Weighted_Random_Early_Detection_WRED.c2026-02-10 16:27 1.9K 
[TXT]__4_4_5__TRAFFIC_CONDITIONING_AND_POLICING.c2026-02-10 16:27 171  
[TXT]__4_4_6__SPANNING_TREE_SUPPORT.c2026-02-10 16:27 6.1K 
[TXT]__4_4_7_1__Discarding_State.c2026-02-10 16:27 945  
[TXT]__4_4_7_2__Learning_State.c2026-02-10 16:27 940  
[TXT]__4_4_7_3__Forwarding_State.c2026-02-10 16:27 1.2K 
[TXT]__4_4_7__RAPID_SPANNING_TREE_SUPPORT.c2026-02-10 16:27 361  
[TXT]__4_4_8__MULTIPLE_SPANNING_TREE_SUPPORT.c2026-02-10 16:27 587  
[TXT]__4_4_9__TAIL_TAGGING_MODE.c2026-02-10 16:27 9.6K 
[TXT]__4_4_10_1__IGMP_Snooping.c2026-02-10 16:27 506  
[TXT]__4_4_10_2__Multicast_Address_Insertion_in_the_Static_MAC_Table.c2026-02-10 16:27 549  
[TXT]__4_4_10__IGMP_SUPPORT.c2026-02-10 16:27 345  
[TXT]__4_4_11__IPV6_MLD_SNOOPING.c2026-02-10 16:27 262  
[TXT]__4_4_12_1__Receive_Only_Mirror_on_a_Port.c2026-02-10 16:27 628  
[TXT]__4_4_12_2__Transmit_Only_Mirror_on_a_Port.c2026-02-10 16:27 544  
[TXT]__4_4_12_3__Receive_and_Transmit_Mirror_on_a_Port.c2026-02-10 16:27 813  
[TXT]__4_4_12__PORT_MIRRORING.c2026-02-10 16:27 367  
[TXT]__4_4_13_1__Strict_Priority_Scheduling.c2026-02-10 16:27 738  
[TXT]__4_4_13_2__Weighted_Round_Robin_WRR_Scheduling.c2026-02-10 16:27 420  
[TXT]__4_4_13_3__Rate_Limiting.c2026-02-10 16:27 2.3K 
[TXT]__4_4_13__SCHEDULING_AND_RATE_LIMITING.c2026-02-10 16:27 379  
[TXT]__4_4_14_1__IEEE_802_1Qav_Credit_Based_Traffic_Shaper.c2026-02-10 16:27 1.8K 
[TXT]__4_4_14_2__Time_Aware_Traffic_Scheduler_TAS.c2026-02-10 16:27 2.4K 
[TXT]__4_4_14__EGRESS_TRAFFIC_SHAPING.c2026-02-10 16:27 2.0K 
[TXT]__4_4_15__LOW_LATENCY_CUT_THROUGH_MODE.c2026-02-10 16:27 2.1K 
[TXT]__4_4_16__INGRESS_MAC_ADDRESS_FILTERING_FUNCTION.c2026-02-10 16:27 871  
[TXT]__4_4_17__802_1X_ACCESS_CONTROL.c2026-02-10 16:27 3.1K 
[TXT]__4_4_18_1__Processing_Entry_Description.c2026-02-10 16:27 9.5K 
[TXT]__4_4_18_2__Matching_Rule_Description.c2026-02-10 16:27 12K 
[TXT]__4_4_18_3__Action_Rule_Description.c2026-02-10 16:27 8.5K 
[TXT]__4_4_18_4__ACL_Interrupts.c2026-02-10 16:27 813  
[TXT]__4_4_18_5__ACL_Registers.c2026-02-10 16:27 1.4K 
[TXT]__4_4_18__ACCESS_CONTROL_LIST_ACL_FILTERING.c2026-02-10 16:27 4.0K 
[TXT]__4_4__Switch.c2026-02-10 16:27 107  
[TXT]__4_5_1__DEVICE_LEVEL_RING_DLR.c2026-02-10 16:27 3.5K 
[TXT]__4_5_2__HIGH_AVAILABILITY_SEAMLESS_REDUNDANCY_HSR.c2026-02-10 16:27 4.3K 
[TXT]__4_5__Ring_Redundancy.c2026-02-10 16:27 715  
[TXT]__4_6_1__IEEE_1588_PTP_SYSTEM_TIME_CLOCK.c2026-02-10 16:27 1.8K 
[TXT]__4_6_2__IEEE_1588_PTP_MESSAGING_PROCESSING.c2026-02-10 16:27 757  
[TXT]__4_6_3__IEEE_1588_PTP_EVENT_TRIGGERING_AND_TIMESTAMPING.c2026-02-10 16:27 632  
[TXT]__4_6__IEEE_1588_Precision_Time_Protocol.c2026-02-10 16:27 2.6K 
[TXT]__4_7__Audio_Video_Bridging_and_Time_Sensitive_Networks.c2026-02-10 16:27 2.9K 
[TXT]__4_8__NAND_Tree_Support.c2026-02-10 16:27 5.8K 
[TXT]__4_9_1__PRIMARY_CLOCK.c2026-02-10 16:27 716  
[TXT]__4_9_2__PORT_6_RGMII_MII_RMII_CLOCKS.c2026-02-10 16:27 1.7K 
[TXT]__4_9_3__PORT_7_SGMII_CLOCK.c2026-02-10 16:27 624  
[TXT]__4_9_4__SERIAL_MANAGEMENT_INTERFACE_CLOCK.c2026-02-10 16:27 352  
[TXT]__4_9_5__SYNCHRONOUS_ETHERNET_AND_SYNCLKO.c2026-02-10 16:27 1.1K 
[TXT]__4_9__Clocking.c2026-02-10 16:27 119  
[TXT]__4_10__Power.c2026-02-10 16:27 1.7K 
[TXT]__4_11_1__NORMAL_OPERATION_MODE.c2026-02-10 16:27 731  
[TXT]__4_11_2__ENERGY_DETECT_MODE.c2026-02-10 16:27 1.3K 
[TXT]__4_11_3__GLOBAL_SOFT_POWER_DOWN_MODE.c2026-02-10 16:27 553  
[TXT]__4_11_4__PORT_BASED_POWER_DOWN.c2026-02-10 16:27 212  
[TXT]__4_11_5_1__Direction_of_Energy.c2026-02-10 16:27 401  
[TXT]__4_11_5_2__Direction_of_Link_up.c2026-02-10 16:27 247  
[TXT]__4_11_5_3__Magic_Packet_TM.c2026-02-10 16:27 2.0K 
[TXT]__4_11_5_4__Interrupt_Generation_on_Power_Management_Events.c2026-02-10 16:27 420  
[TXT]__4_11_5__WAKE_ON_LAN_WOL.c2026-02-10 16:27 1.2K 
[TXT]__4_11__Power_Management.c2026-02-10 16:27 2.2K 
[TXT]__4_12_1__SPI_SLAVE_BUS.c2026-02-10 16:27 5.3K 
[TXT]__4_12_2__I2C_BUS.c2026-02-10 16:27 4.1K 
[TXT]__4_12_3_1__Standard_MIIM_Registers_Direct.c2026-02-10 16:27 6.8K 
[TXT]__4_12_3_2__MDIO_Manageable_Device_MMD_Registers_Indirect.c2026-02-10 16:27 382  
[TXT]__4_12_3__MII_MANAGEMENT_MIIM_INTERFACE.c2026-02-10 16:27 3.3K 
[TXT]__4_12__Management_Interface.c2026-02-10 16:27 1.0K 
[TXT]__4_13__In_Band_Management.c2026-02-10 16:27 5.5K 
[TXT]__4_14_1__MEDIA_INDEPENDENT_INTERFACE_MII_PORT_6.c2026-02-10 16:27 6.9K 
[TXT]__4_14_2__REDUCED_MEDIA_INDEPENDENT_INTERFACE_RMII_PORT_6.c2026-02-10 16:27 8.2K 
[TXT]__4_14_3__REDUCED_GIGABIT_MEDIA_INDEPENDENT_INTERFACE_RGMII_PORT_6.c2026-02-10 16:27 5.7K 
[TXT]__4_14_4__SERIAL_GIGABIT_MEDIA_INDEPENDENT_INTERFACE_SGMII_PORT_7.c2026-02-10 16:27 4.0K 
[TXT]__4_14__MAC_Interface_Ports_6_and_7.c2026-02-10 16:27 1.3K 
[TXT]__5_0__DEVICE_REGISTERS.c2026-02-10 16:27 14K 
[TXT]__5_1_1_6__0x0010_0x0013_32_Global_Interrupt_Status_Register.c2026-02-10 16:27 2.5K 
[TXT]__5_1_1_7__0x0014_0x0017_32_Global_Interrupt_Mask_Register.c2026-02-10 16:27 1.6K 
[TXT]__5_1_1_8__0x0018_0x001B_32_Global_Port_Interrupt_Status_Register.c2026-02-10 16:27 2.3K 
[TXT]__5_1_1_9__0x001C_0x001F_32_Global_Port_Interrupt_Mask_Register.c2026-02-10 16:27 2.2K 
[TXT]__5_1_1__GLOBAL_OPERATION_CONTROL_REGISTERS.c2026-02-10 16:27 397  
[TXT]__5_1_2_1__0x0100_0x0100_08_Serial_IO_Control_Register.c2026-02-10 16:27 2.9K 
[TXT]__5_1_2_2__0x0103_0x0103_08_Output_Clock_Control_Register.c2026-02-10 16:27 2.8K 
[TXT]__5_1_2_3__0x0104_0x0107_32_In_Band_Management_IBA_Control_Register.c2026-02-10 16:27 4.4K 
[TXT]__5_1_2_4__0x010D_0x010D_08_I_O_Drive_Strength_Register.c2026-02-10 16:27 1.7K 
[TXT]__5_1_2_5__0x0110_0x0113_32_In_Band_Management_IBA_Operation_Status_1_Register.c2026-02-10 16:27 5.9K 
[TXT]__5_1_2_6__0x0120_0x0123_32_LED_Override_Register.c2026-02-10 16:27 1.7K 
[TXT]__5_1_2_7__0x0124_0x0127_32_LED_Output_Register.c2026-02-10 16:27 1.5K 
[TXT]__5_1_2_8__0x0128_0x012B_32_LED2_0_LED2_1_Source_Register.c2026-02-10 16:27 2.0K 
[TXT]__5_1_2__GLOBAL_IO_CONTROL_REGISTERS.c2026-02-10 16:27 156  
[TXT]__5_1_3_1__0x0201_0x0201_08_Power_Down_Control_0_Register.c2026-02-10 16:27 2.5K 
[TXT]__5_1_3_2__0x0210_0x0213_32_LED_Configuration_Strap_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_3__GLOBAL_PHY_CONTROL_AND_STATUS_REGISTERS.c2026-02-10 16:27 197  
[TXT]__5_1_4_1__0x0300_0x0300_08_Switch_Operation_Register.c2026-02-10 16:27 2.2K 
[TXT]__5_1_4_2__0x0302_0x0302_08_Switch_MAC_Address_0_Register.c2026-02-10 16:27 1.0K 
[TXT]__5_1_4_3__0x0303_0x0303_08_Switch_MAC_Address_1_Register.c2026-02-10 16:27 730  
[TXT]__5_1_4_4__0x0304_0x0304_08_Switch_MAC_Address_2_Register.c2026-02-10 16:27 725  
[TXT]__5_1_4_5__0x0305_0x0305_08_Switch_MAC_Address_3_Register.c2026-02-10 16:27 730  
[TXT]__5_1_4_6__0x0306_0x0306_08_Switch_MAC_Address_4_Register.c2026-02-10 16:27 730  
[TXT]__5_1_4_7__0x0307_0x0307_08_Switch_MAC_Address_5_Register.c2026-02-10 16:27 495  
[TXT]__5_1_4_8__0x0308_0x0309_16_Switch_Maximum_Transmit_Unit_Register.c2026-02-10 16:27 1.4K 
[TXT]__5_1_4_9__0x030A_0x030B_16_Switch_ISP_TPID_Register.c2026-02-10 16:27 941  
[TXT]__5_1_4_10__0x030C_0x030D_16_Switch_HSR_TPID_Register.c2026-02-10 16:27 840  
[TXT]__5_1_4_11__0x030E_0x030F_16_AVB_Credit_Based_Shaper_Strategy_Register.c2026-02-10 16:27 1.6K 
[TXT]__5_1_4_12__0x0310_0x0310_08_Switch_Lookup_Engine_Control_0_Register.c2026-02-10 16:27 3.7K 
[TXT]__5_1_4_13__0x0311_0x0311_08_Switch_Lookup_Engine_Control_1_Register.c2026-02-10 16:27 4.7K 
[TXT]__5_1_4_14__0x0312_0x0312_08_Switch_Lookup_Engine_Control_2_Register.c2026-02-10 16:27 4.3K 
[TXT]__5_1_4_15__0x0313_0x0313_08_Switch_Lookup_Engine_Control_3_Register.c2026-02-10 16:27 1.0K 
[TXT]__5_1_4_16__0x0314_0x0314_08_Address_Lookup_Table_Interrupt_Register.c2026-02-10 16:27 2.2K 
[TXT]__5_1_4_17__0x0315_0x0315_08_Address_Lookup_Table_Mask_Register.c2026-02-10 16:27 2.0K 
[TXT]__5_1_4_18__0x0316_0x0317_16_Address_Lookup_Table_Entry_Index_0_Register.c2026-02-10 16:27 1.7K 
[TXT]__5_1_4_19__0x0318_0x0319_16_Address_Lookup_Table_Entry_Index_1_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_20__0x031A_0x031B_16_Address_Lookup_Table_Entry_Index_2_Register.c2026-02-10 16:27 1.2K 
[TXT]__5_1_4_21__0x0320_0x0323_32_Unknown_Unicast_Control_Register.c2026-02-10 16:27 2.3K 
[TXT]__5_1_4_22__0x0324_0x0327_32_Unknown_Multicast_Control_Register.c2026-02-10 16:27 2.0K 
[TXT]__5_1_4_23__0x0328_0x032B_32_Unknown_VLAN_ID_Control_Register.c2026-02-10 16:27 2.0K 
[TXT]__5_1_4_24__0x0330_0x0330_08_Switch_MAC_Control_0_Register.c2026-02-10 16:27 3.5K 
[TXT]__5_1_4_25__0x0331_0x0331_08_Switch_MAC_Control_1_Register.c2026-02-10 16:27 4.2K 
[TXT]__5_1_4_26__0x0332_0x0332_08_Switch_MAC_Control_2_Register.c2026-02-10 16:27 2.1K 
[TXT]__5_1_4_27__0x0333_0x0333_08_Switch_MAC_Control_3_Register.c2026-02-10 16:27 1.2K 
[TXT]__5_1_4_28__0x0334_0x0334_08_Switch_MAC_Control_4_Register.c2026-02-10 16:27 1.1K 
[TXT]__5_1_4_29__0x0335_0x0335_08_Switch_MAC_Control_5_Register.c2026-02-10 16:27 2.0K 
[TXT]__5_1_4_30__0x0336_0x0336_08_Switch_MIB_Control_Register.c2026-02-10 16:27 1.9K 
[TXT]__5_1_4_31__0x0338_0x0338_08_802_1p_Priority_Mapping_0_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_32__0x0339_0x0339_08_802_1p_Priority_Mapping_1_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_33__0x033A_0x033A_08_802_1p_Priority_Mapping_2_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_34__0x033B_0x033B_08_802_1p_Priority_Mapping_3_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_35__0x033E_0x033E_08_IP_DiffServ_Priority_Enable_Register.c2026-02-10 16:27 1.4K 
[TXT]__5_1_4_36__0x0340_0x0340_08_IP_DiffServ_Priority_Mapping_0_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_37__0x0341_0x0341_08_IP_DiffServ_Priority_Mapping_1_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_38__0x0342_0x0342_08_IP_DiffServ_Priority_Mapping_2_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_39__0x0343_0x0343_08_IP_DiffServ_Priority_Mapping_3_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_40__0x0344_0x0344_08_IP_DiffServ_Priority_Mapping_4_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_41__0x0345_0x0345_08_IP_DiffServ_Priority_Mapping_5_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_42__0x0346_0x0346_08_IP_DiffServ_Priority_Mapping_6_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_43__0x0347_0x0347_08_IP_DiffServ_Priority_Mapping_7_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_44__0x0348_0x0348_08_IP_DiffServ_Priority_Mapping_8_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_45__0x0349_0x0349_08_IP_DiffServ_Priority_Mapping_9_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_46__0x034A_0x034A_08_IP_DiffServ_Priority_Mapping_10_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_47__0x034B_0x034B_08_IP_DiffServ_Priority_Mapping_11_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_48__0x034C_0x034C_08_IP_DiffServ_Priority_Mapping_12_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_49__0x034D_0x034D_08_IP_DiffServ_Priority_Mapping_13_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_50__0x034E_0x034E_08_IP_DiffServ_Priority_Mapping_14_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_51__0x034F_0x034F_08_IP_DiffServ_Priority_Mapping_15_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_52__0x0350_0x0350_08_IP_DiffServ_Priority_Mapping_16_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_53__0x0351_0x0351_08_IP_DiffServ_Priority_Mapping_17_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_54__0x0352_0x0352_08_IP_DiffServ_Priority_Mapping_18_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_55__0x0353_0x0353_08_IP_DiffServ_Priority_Mapping_19_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_56__0x0354_0x0354_08_IP_DiffServ_Priority_Mapping_20_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_57__0x0355_0x0355_08_IP_DiffServ_Priority_Mapping_21_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_58__0x0356_0x0356_08_IP_DiffServ_Priority_Mapping_22_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_59__0x0357_0x0357_08_IP_DiffServ_Priority_Mapping_23_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_60__0x0358_0x0358_08_IP_DiffServ_Priority_Mapping_24_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_61__0x0359_0x0359_08_IP_DiffServ_Priority_Mapping_25_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_62__0x035A_0x035A_08_IP_DiffServ_Priority_Mapping_26_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_63__0x035B_0x035B_08_IP_DiffServ_Priority_Mapping_27_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_64__0x035C_0x035C_08_IP_DiffServ_Priority_Mapping_28_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_65__0x035D_0x035D_08_IP_DiffServ_Priority_Mapping_29_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_66__0x035E_0x035E_08_IP_DiffServ_Priority_Mapping_30_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_67__0x035F_0x035F_08_IP_DiffServ_Priority_Mapping_31_Register.c2026-02-10 16:27 1.3K 
[TXT]__5_1_4_68__0x0370_0x0370_08_Global_Port_Mirroring_and_Snooping_Control_Register.c2026-02-10 16:27 3.7K 
[TXT]__5_1_4_69__0x0378_0x0378_08_WRED_DiffServ_Color_Mapping_Register.c2026-02-10 16:27 1.7K 
[TXT]__5_1_4_70__0x037C_0x037C_08_PTP_Event_Message_Priority_Register.c2026-02-10 16:27 1.6K 
[TXT]__5_1_4_71__0x037D_0x037D_08_PTP_Non_Event_Message_Priority_Register.c2026-02-10 16:27 1.6K 
[TXT]__5_1_4_72__0x0390_0x0393_32_Queue_Management_Control_0_Register.c2026-02-10 16:27 3.4K 
[TXT]__5_1_4__GLOBAL_SWITCH_CONTROL_REGISTERS.c2026-02-10 16:27 181  
[TXT]__5_1_5_1__0x0400_0x0403_32_VLAN_Table_Entry_0_Register.c2026-02-10 16:27 3.9K 
[TXT]__5_1_5_2__0x0404_0x0407_32_VLAN_Table_Entry_1_Register.c2026-02-10 16:27 1.6K 
[TXT]__5_1_5_3__0x0408_0x040B_32_VLAN_Table_Entry_2_Register.c2026-02-10 16:27 1.6K 
[TXT]__5_1_5_4__0x040C_0x040D_16_VLAN_Table_Index_Register.c2026-02-10 16:27 1.2K 
[TXT]__5_1_5_5__0x040E_0x040E_08_VLAN_Table_Access_Control_Register.c2026-02-10 16:27 2.0K 
[TXT]__5_1_5_6__0x0410_0x0413_32_ALU_Table_Index_0_Register.c2026-02-10 16:28 2.0K 
[TXT]__5_1_5_7__0x0414_0x0417_32_ALU_Table_Index_1_Register.c2026-02-10 16:28 1.4K 
[TXT]__5_1_5_8__0x0418_0x041B_32_ALU_Table_Access_Control_Register.c2026-02-10 16:28 5.4K 
[TXT]__5_1_5_9__0x041C_0x041F_32_Static_Address_and_Reserved_Multicast_Table_Control_Register.c2026-02-10 16:28 3.8K 
[TXT]__5_1_5_10__0x0420_0x0423_32_ALU_Static_Address_Table_Entry_1_Register.c2026-02-10 16:28 798  
[TXT]__5_1_5_11__0x0424_0x0427_32_ALU_Static_Address_Reserved_Multicast_Table_Entry_2_Register.c2026-02-10 16:28 829  
[TXT]__5_1_5_12__0x0428_0x042B_32_ALU_Static_Address_Table_Entry_3_Register.c2026-02-10 16:28 652  
[TXT]__5_1_5_13__0x042C_0x042F_32_ALU_Static_Address_Table_Entry_4_Register.c2026-02-10 16:28 800  
[TXT]__5_1_5_14__0x0444_0x0447_32_Global_HSR_ALU_Index_Register_1.c2026-02-10 16:28 1.6K 
[TXT]__5_1_5_15__0x0448_0x044B_32_Global_HSR_ALU_Index_Register_2.c2026-02-10 16:28 1.5K 
[TXT]__5_1_5_16__0x0450_0x0453_32_Global_HSR_ALU_Access_Control_Register.c2026-02-10 16:28 4.3K 
[TXT]__5_1_5_17__0x0454_0x0457_32_Global_HSR_ALU_Value_A_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_5_18__0x0458_0x045B_32_Global_HSR_ALU_Value_B_Register.c2026-02-10 16:28 1.6K 
[TXT]__5_1_5_19__0x045C_0x045F_32_Global_HSR_ALU_Value_C_Register.c2026-02-10 16:28 1.6K 
[TXT]__5_1_5_20__0x0460_0x0463_32_Global_HSR_ALU_Value_D_Register.c2026-02-10 16:28 1.4K 
[TXT]__5_1_5_21__0x0464_0x0467_32_Global_HSR_ALU_Value_E_Register.c2026-02-10 16:28 1.6K 
[TXT]__5_1_5_22__0x0468_0x046B_32_Global_HSR_ALU_Value_F_Register.c2026-02-10 16:28 1.6K 
[TXT]__5_1_5_23__0x046C_0x046F_32_Global_HSR_ALU_Value_G_Register.c2026-02-10 16:28 1.6K 
[TXT]__5_1_5__GLOBAL_SWITCH_LOOK_UP_ENGINE_LUE_CONTROL_REGISTERS.c2026-02-10 16:27 529  
[TXT]__5_1_6_1__0x0500_0x0501_16_Global_PTP_Clock_Control_Register.c2026-02-10 16:28 5.1K 
[TXT]__5_1_6_2__0x0502_0x0503_16_Global_PTP_RTC_Clock_Phase_Register.c2026-02-10 16:28 1.9K 
[TXT]__5_1_6_3__0x0504_0x0505_16_Global_PTP_RTC_Clock_Nanosecond_High_Word_Register.c2026-02-10 16:28 1.0K 
[TXT]__5_1_6_4__0x0506_0x0507_16_Global_PTP_RTC_Clock_Nanosecond_Low_Word_Register.c2026-02-10 16:28 1.0K 
[TXT]__5_1_6_5__0x0508_0x0509_16_Global_PTP_RTC_Clock_Second_High_Word_Register.c2026-02-10 16:28 876  
[TXT]__5_1_6_6__0x050A_0x050B_16_Global_PTP_RTC_Clock_Second_Low_Word_Register.c2026-02-10 16:28 874  
[TXT]__5_1_6_7__0x050C_0x050D_16_Global_PTP_Clock_Sub_Nanosecond_Rate_High_Word_Register.c2026-02-10 16:28 2.8K 
[TXT]__5_1_6_8__0x050E_0x050F_16_Global_PTP_Clock_Sub_Nanosecond_Rate_Low_Word_Register.c2026-02-10 16:28 1.1K 
[TXT]__5_1_6_9__0x0510_0x0511_16_Global_PTP_Clock_Temp_Adjustment_Duration_High_Word_Register.c2026-02-10 16:28 1.0K 
[TXT]__5_1_6_10__0x0512_0x0513_16_Global_PTP_Clock_Temp_Adjustment_Duration_Low_Word_Register.c2026-02-10 16:28 1.0K 
[TXT]__5_1_6_11__0x0514_0x0515_16_Global_PTP_Message_Config_1_Register.c2026-02-10 16:28 4.9K 
[TXT]__5_1_6_12__0x0516_0x0517_16_Global_PTP_Message_Config_2_Register.c2026-02-10 16:28 7.4K 
[TXT]__5_1_6_13__0x0518_0x0519_16_Global_PTP_Domain_and_Version_Register.c2026-02-10 16:28 2.2K 
[TXT]__5_1_6_14__0x0520_0x0523_32_Global_PTP_Unit_Index_Register.c2026-02-10 16:28 2.4K 
[TXT]__5_1_6_15__0x0524_0x0527_32_GPIO_Status_Monitor_0_Register.c2026-02-10 16:28 2.9K 
[TXT]__5_1_6_16__0x0528_0x052B_32_GPIO_Status_Monitor_1_Register.c2026-02-10 16:28 3.7K 
[TXT]__5_1_6_17__0x052C_0x052F_32_Timestamp_Control_and_Status_Register.c2026-02-10 16:28 6.7K 
[TXT]__5_1_6_18__0x0530_0x0533_32_Trigger_Output_Unit_Target_Time_Nanosecond_Register.c2026-02-10 16:28 1.4K 
[TXT]__5_1_6_19__0x0534_0x0537_32_Trigger_Output_Unit_Target_Time_Second_Register.c2026-02-10 16:28 1.1K 
[TXT]__5_1_6_20__0x0538_0x053B_32_Trigger_Output_Unit_Control_1_Register.c2026-02-10 16:28 8.7K 
[TXT]__5_1_6_21__0x053C_0x053F_32_Trigger_Output_Unit_Control_2_Register.c2026-02-10 16:28 971  
[TXT]__5_1_6_22__0x0540_0x0543_32_Trigger_Output_Unit_Control_3_Register.c2026-02-10 16:28 1.7K 
[TXT]__5_1_6_23__0x0544_0x0547_32_Trigger_Output_Unit_Control_4_Register.c2026-02-10 16:28 1.7K 
[TXT]__5_1_6_24__0x0548_0x054B_32_Trigger_Output_Unit_Control_5_Register.c2026-02-10 16:28 2.5K 
[TXT]__5_1_6_25__0x0550_0x0553_32_Timestamp_Status_and_Control_Register.c2026-02-10 16:28 6.5K 
[TXT]__5_1_6_26__0x0554_0x0557_32_Timestamp_1st_Sample_Time_Nanoseconds_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_1_6_27__0x0558_0x055B_32_Timestamp_1st_Sample_Time_Seconds_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_1_6_28__0x055C_0x055F_32_Timestamp_1st_Sample_Time_Phase_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_6_29__0x0560_0x0563_32_Timestamp_2nd_Sample_Time_Nanoseconds_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_1_6_30__0x0564_0x0567_32_Timestamp_2nd_Sample_Time_Seconds_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_1_6_31__0x0568_0x056F_32_Timestamp_2nd_Sample_Time_Phase_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_6_32__0x056C_0x056F_32_Timestamp_3rd_Sample_Time_Nanoseconds_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_1_6_33__0x0570_0x0573_32_Timestamp_3rd_Sample_Time_Seconds_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_1_6_34__0x0574_0x0577_32_Timestamp_3rd_Sample_Time_Phase_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_6_35__0x0578_0x057B_32_Timestamp_4th_Sample_Time_Nanoseconds_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_1_6_36__0x057C_0x057F_32_Timestamp_4th_Sample_Time_Seconds_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_1_6_37__0x0580_0x0583_32_Timestamp_4th_Sample_Time_Phase_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_6_38__0x0584_0x0587_32_Timestamp_5th_Sample_Time_Nanoseconds_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_1_6_39__0x0588_0x058B_32_Timestamp_5th_Sample_Time_Seconds_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_1_6_40__0x058C_0x058F_32_Timestamp_5th_Sample_Time_Phase_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_6_41__0x0590_0x0593_32_Timestamp_6th_Sample_Time_Nanoseconds_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_1_6_42__0x0594_0x0597_32_Timestamp_6th_Sample_Time_Seconds_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_1_6_43__0x0598_0x059B_32_Timestamp_6th_Sample_Time_Phase_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_6_44__0x059C_0x059F_32_Timestamp_7th_Sample_Time_Nanoseconds_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_1_6_45__0x05A0_0x05A3_32_Timestamp_7th_Sample_Time_Seconds_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_1_6_46__0x05A4_0x05A7_32_Timestamp_7th_Sample_Time_Phase_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_6_47__0x05A8_0x05AB_32_Timestamp_8th_Sample_Time_Nanoseconds_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_1_6_48__0x05AC_0x05AF_32_Timestamp_8th_Sample_Time_Seconds_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_1_6_49__0x05B0_0x05B3_32_Timestamp_8th_Sample_Time_Phase_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_6__GLOBAL_SWITCH_PTP_CONTROL_REGISTERS.c2026-02-10 16:28 185  
[TXT]__5_1_7_1__0x0604_0x0607_32_Global_DLR_Source_Port_Register.c2026-02-10 16:28 2.0K 
[TXT]__5_1_7_2__0x0608_0x060B_32_Global_DLR_Source_IP_Address_Register.c2026-02-10 16:28 972  
[TXT]__5_1_7_3__0x0610_0x0610_08_Global_DLR_Control_Register.c2026-02-10 16:28 4.0K 
[TXT]__5_1_7_4__0x0611_0x0611_08_Global_DLR_State_Register.c2026-02-10 16:28 2.2K 
[TXT]__5_1_7_5__0x0612_0x0612_08_Global_DLR_Supervisor_Precedent_Register.c2026-02-10 16:28 1.0K 
[TXT]__5_1_7_6__0x0614_0x0617_32_Global_DLR_Beacon_Interval_Register.c2026-02-10 16:28 1.1K 
[TXT]__5_1_7_7__0x0618_0x061B_32_Global_DLR_Beacon_Timeout_Register.c2026-02-10 16:28 1.4K 
[TXT]__5_1_7_8__0x061C_0x061F_32_Global_DLR_Beacon_Timeout_Window_Register.c2026-02-10 16:28 1.6K 
[TXT]__5_1_7_9__0x0620_0x0621_16_Global_DLR_VLAN_ID_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_1_7_10__0x0622_0x0627_48_Global_DLR_Destination_Address_Register.c2026-02-10 16:28 1.1K 
[TXT]__5_1_7_11__0x0628_0x062B_32_Global_DLR_Port_Map_Register.c2026-02-10 16:28 1.3K 
[TXT]__5_1_7_12__0x062C_0x062C_08_Global_DLR_Class_Register.c2026-02-10 16:28 1.3K 
[TXT]__5_1_7_13__0x0640_0x0643_32_Global_HSR_Port_Map_Register.c2026-02-10 16:28 1.3K 
[TXT]__5_1_7_14__0x0644_0x0644_08_Global_HSR_AME_Control_Register_0.c2026-02-10 16:28 3.1K 
[TXT]__5_1_7_15__0x0645_0x0645_08_Global_HSR_AME_Control_Register_1.c2026-02-10 16:28 3.7K 
[TXT]__5_1_7_16__0x0648_0x064B_32_Global_HSR_AME_Age_Period_Register.c2026-02-10 16:28 1.7K 
[TXT]__5_1_7_17__0x064C_0x064C_08_Global_HSR_AME_Interrupt_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_1_7_18__0x064D_0x064D_08_Global_HSR_AME_Interrupt_Mask_Register.c2026-02-10 16:28 2.3K 
[TXT]__5_1_7__GLOBAL_SWITCH_RING_REDUNDANCY_CONTROL_REGISTERS.c2026-02-10 16:28 213  
[TXT]__5_1__GLOBAL_REGISTERS_OVERVIEW.c2026-02-10 16:27 408  
[TXT]__5_2_1_1__0xN000_0xN000_08_Port_Default_Tag_0_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_2_1_2__0xN001_0xN001_08_Port_Default_Tag_1_Register.c2026-02-10 16:28 1.0K 
[TXT]__5_2_1_3__0xN013_0xN013_08_Port_PME_WoL_Event_Register.c2026-02-10 16:28 2.8K 
[TXT]__5_2_1_4__0xN017_0xN017_08_Port_PME_WoL_Enable_Register.c2026-02-10 16:28 3.0K 
[TXT]__5_2_1_5__0xN01B_0xN01B_08_Port_Interrupt_Status_Register.c2026-02-10 16:28 4.0K 
[TXT]__5_2_1_6__0xN01F_0xN01F_08_Port_Interrupt_Mask_Register.c2026-02-10 16:28 3.4K 
[TXT]__5_2_1_7__0xN020_0xN020_08_Port_Operation_Control_0_Register.c2026-02-10 16:28 4.5K 
[TXT]__5_2_1_8__0xN030_0xN030_08_Port_Status_Register.c2026-02-10 16:28 5.1K 
[TXT]__5_2_1__PORT_N_PORT_OPERATION_CONTROL_REGISTERS.c2026-02-10 16:28 200  
[TXT]__5_2_2_1__0xN100_0xN101_16_PHY_Basic_Control_Register.c2026-02-10 16:28 7.8K 
[TXT]__5_2_2_2__0xN102_0xN103_16_PHY_Basic_Status_Register.c2026-02-10 16:28 6.3K 
[TXT]__5_2_2_3__0xN104_0xN105_16_PHY_ID_High_Register.c2026-02-10 16:28 866  
[TXT]__5_2_2_4__0xN106_0xN107_16_PHY_ID_Low_Register.c2026-02-10 16:28 864  
[TXT]__5_2_2_5__0xN108_0xN109_16_PHY_Auto_Negotiation_Advertisement_Register.c2026-02-10 16:28 5.7K 
[TXT]__5_2_2_6__0xN10A_0xN10B_16_PHY_Auto_Negotiation_Link_Partner_Ability_Register.c2026-02-10 16:28 5.7K 
[TXT]__5_2_2_7__0xN10C_0xN10D_16_PHY_Auto_Negotiation_Expansion_Status_Register.c2026-02-10 16:28 3.6K 
[TXT]__5_2_2_8__0xN10E_0xN10F_16_PHY_Auto_Negotiation_Next_Page_Register.c2026-02-10 16:28 3.0K 
[TXT]__5_2_2_9__0xN110_0xN111_16_PHY_Auto_Negotiation_Link_Partner_Next_Page_Ability_Register.c2026-02-10 16:28 3.3K 
[TXT]__5_2_2_10__0xN112_0xN113_16_PHY_1000BASE_T_Control_Register.c2026-02-10 16:28 5.5K 
[TXT]__5_2_2_11__0xN114_0xN115_16_PHY_1000BASE_T_Status_Register.c2026-02-10 16:28 5.2K 
[TXT]__5_2_2_12__0xN11A_0xN11B_16_PHY_MMD_Setup_Register.c2026-02-10 16:28 2.4K 
[TXT]__5_2_2_13__0xN11C_0xN11D_16_PHY_MMD_Data_Register.c2026-02-10 16:28 1.9K 
[TXT]__5_2_2_14__0xN11E_0xN11F_16_PHY_Extended_Status_Register.c2026-02-10 16:28 2.9K 
[TXT]__5_2_2_15__0xN122_0xN123_16_PHY_Remote_Loopback_Register.c2026-02-10 16:28 2.5K 
[TXT]__5_2_2_16__0xN124_0xN125_16_PHY_LinkMD_Register.c2026-02-10 16:28 4.7K 
[TXT]__5_2_2_17__0xN126_0xN127_16_PHY_Digital_PMA_PCS_Status_Register.c2026-02-10 16:28 1.9K 
[TXT]__5_2_2_18__0xN12A_0xN12B_16_Port_RXER_Count_Register.c2026-02-10 16:28 1.0K 
[TXT]__5_2_2_19__0xN136_0xN137_16_Port_Interrupt_Control_Status_Register.c2026-02-10 16:28 8.6K 
[TXT]__5_2_2_20__0xN138_0xN139_16_PHY_Auto_MDI_MDI_X_Register.c2026-02-10 16:28 2.4K 
[TXT]__5_2_2_21__0xN13E_0xN13F_16_PHY_Control_Register.c2026-02-10 16:28 4.5K 
[TXT]__5_2_2__PORT_N_PORT_ETHERNET_PHY_REGISTERS.c2026-02-10 16:28 305  
[TXT]__5_2_3_1__0xN200_0xN203_32_Port_SGMII_Address_Register.c2026-02-10 16:28 2.7K 
[TXT]__5_2_3_2__0xN206_0xN207_16_Port_SGMII_Data_Register.c2026-02-10 16:28 902  
[TXT]__5_2_3__PORT_N_PORT_SGMII_CONTROL_REGISTERS.c2026-02-10 16:28 1.1K 
[TXT]__5_2_4_1__0xN300_0xN300_08_XMII_Port_Control_0_Register.c2026-02-10 16:28 3.9K 
[TXT]__5_2_4_2__0xN301_0xN301_08_XMII_Port_Control_1_Register.c2026-02-10 16:28 4.7K 
[TXT]__5_2_4__PORT_N_PORT_RGMII_MII_RMII_CONTROL_REGISTERS.c2026-02-10 16:28 252  
[TXT]__5_2_5_1__0xN400_0xN400_08_Port_MAC_Control_0_Register.c2026-02-10 16:28 2.2K 
[TXT]__5_2_5_2__0xN401_0xN401_08_Port_MAC_Control_1_Register.c2026-02-10 16:28 3.5K 
[TXT]__5_2_5_3__0xN403_0xN403_08_Port_Ingress_Rate_Limit_Control_Register.c2026-02-10 16:28 5.4K 
[TXT]__5_2_5_4__0xN410_0xN410_08_Port_Priority_0_Ingress_Limit_Control_Register.c2026-02-10 16:28 5.3K 
[TXT]__5_2_5_5__0xN411_0xN411_08_Port_Priority_1_Ingress_Limit_Control_Register.c2026-02-10 16:28 1.5K 
[TXT]__5_2_5_6__0xN412_0xN412_08_Port_Priority_2_Ingress_Limit_Control_Register.c2026-02-10 16:28 1.5K 
[TXT]__5_2_5_7__0xN413_0xN413_08_Port_Priority_3_Ingress_Limit_Control_Register.c2026-02-10 16:28 1.5K 
[TXT]__5_2_5_8__0xN414_0xN414_08_Port_Priority_4_Ingress_Limit_Control_Register.c2026-02-10 16:28 1.5K 
[TXT]__5_2_5_9__0xN415_0xN415_08_Port_Priority_5_Ingress_Limit_Control_Register.c2026-02-10 16:28 1.5K 
[TXT]__5_2_5_10__0xN416_0xN416_08_Port_Priority_6_Ingress_Limit_Control_Register.c2026-02-10 16:28 1.5K 
[TXT]__5_2_5_11__0xN417_0xN417_08_Port_Priority_7_Ingress_Limit_Control_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_2_5_12__0xN420_0xN420_08_Port_Queue_0_Egress_Limit_Control_Register.c2026-02-10 16:28 2.0K 
[TXT]__5_2_5_13__0xN421_0xN421_08_Port_Queue_1_Egress_Limit_Control_Register.c2026-02-10 16:28 1.5K 
[TXT]__5_2_5_14__0xN422_0xN422_08_Port_Queue_2_Egress_Limit_Control_Register.c2026-02-10 16:28 1.5K 
[TXT]__5_2_5_15__0xN423_0xN423_08_Port_Queue_3_Egress_Limit_Control_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_2_5__PORT_N_PORT_SWITCH_MAC_CONTROL_REGISTERS.c2026-02-10 16:28 244  
[TXT]__5_2_6_1__0xN500_0xN503_32_Port_MIB_Control_and_Status_Register.c2026-02-10 16:28 3.7K 
[TXT]__5_2_6_2__0xN504_0xN507_32_Port_MIB_Data_Register.c2026-02-10 16:28 930  
[TXT]__5_2_6__PORT_N_PORT_SWITCH_MIB_COUNTERS_REGISTERS.c2026-02-10 16:28 583  
[TXT]__5_2_7_1__0xN600_0xN600_08_Port_ACL_Access_0_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_2_7_2__0xN601_0xN601_08_Port_ACL_Access_1_Register.c2026-02-10 16:28 3.0K 
[TXT]__5_2_7_3__0xN602_0xN602_08_Port_ACL_Access_2_Register.c2026-02-10 16:28 942  
[TXT]__5_2_7_4__0xN603_0xN603_08_Port_ACL_Access_3_Register.c2026-02-10 16:28 937  
[TXT]__5_2_7_5__0xN604_0xN604_08_Port_ACL_Access_4_Register.c2026-02-10 16:28 937  
[TXT]__5_2_7_6__0xN605_0xN605_08_Port_ACL_Access_5_Register.c2026-02-10 16:28 937  
[TXT]__5_2_7_7__0xN606_0xN606_08_Port_ACL_Access_6_Register.c2026-02-10 16:28 937  
[TXT]__5_2_7_8__0xN607_0xN607_08_Port_ACL_Access_7_Register.c2026-02-10 16:28 942  
[TXT]__5_2_7_9__0xN608_0xN608_08_Port_ACL_Access_8_Register.c2026-02-10 16:28 942  
[TXT]__5_2_7_10__0xN609_0xN609_08_Port_ACL_Access_9_Register.c2026-02-10 16:28 944  
[TXT]__5_2_7_11__0xN60A_0xN60A_08_Port_ACL_Access_A_Register.c2026-02-10 16:28 2.0K 
[TXT]__5_2_7_12__0xN60B_0xN60B_08_Port_ACL_Access_B_Register.c2026-02-10 16:28 1.7K 
[TXT]__5_2_7_13__0xN60C_0xN60C_08_Port_ACL_Access_C_Register.c2026-02-10 16:28 944  
[TXT]__5_2_7_14__0xN60D_0xN60D_08_Port_ACL_Access_D_Register.c2026-02-10 16:28 1.8K 
[TXT]__5_2_7_15__0xN60E_0xN60E_08_Port_ACL_Access_E_Register.c2026-02-10 16:28 944  
[TXT]__5_2_7_16__0xN60F_0xN60F_08_Port_ACL_Access_F_Register.c2026-02-10 16:28 944  
[TXT]__5_2_7_17__0xN610_0xN610_08_Port_ACL_Byte_Enable_MSB_Register.c2026-02-10 16:28 1.9K 
[TXT]__5_2_7_18__0xN611_0xN611_08_Port_ACL_Byte_Enable_LSB_Register.c2026-02-10 16:28 1.9K 
[TXT]__5_2_7_19__0xN612_0xN612_08_Port_ACL_Access_Control_0_Register.c2026-02-10 16:28 2.9K 
[TXT]__5_2_7_20__0xN613_0xN613_08_Port_ACL_Access_Control_1_Register.c2026-02-10 16:28 1.7K 
[TXT]__5_2_7__PORT_N_PORT_SWITCH_ACL_CONTROL_REGISTERS.c2026-02-10 16:28 453  
[TXT]__5_2_8_1__0xN800_0xN800_08_Port_Mirroring_Control_Register.c2026-02-10 16:28 3.6K 
[TXT]__5_2_8_2__0xN801_0xN801_08_Port_Priority_Control_Register.c2026-02-10 16:28 4.7K 
[TXT]__5_2_8_3__0xN802_0xN802_08_Port_Ingress_MAC_Control_Register.c2026-02-10 16:28 3.7K 
[TXT]__5_2_8_4__0xN803_0xN803_08_Port_Authentication_Control_Register.c2026-02-10 16:28 2.8K 
[TXT]__5_2_8_5__0xN804_0xN807_32_Port_Pointer_Register.c2026-02-10 16:28 2.0K 
[TXT]__5_2_8_6__0xN808_0xN80B_32_Port_Priority_to_Queue_Mapping_Register.c2026-02-10 16:28 3.8K 
[TXT]__5_2_8_7__0xN80C_0xN80F_32_Port_Police_Control_Register.c2026-02-10 16:28 6.8K 
[TXT]__5_2_8_8__0xN820_0xN823_32_Port_Police_Queue_Rate_Register.c2026-02-10 16:28 1.7K 
[TXT]__5_2_8_9__0xN824_0xN827_32_Port_Police_Queue_Burst_Size_Register.c2026-02-10 16:28 1.7K 
[TXT]__5_2_8_10__0xN830_0xN833_32_Port_WRED_Packet_Memory_Control_Register_0.c2026-02-10 16:28 1.7K 
[TXT]__5_2_8_11__0xN834_0xN837_32_Port_WRED_Packet_Memory_Control_Register_1.c2026-02-10 16:28 1.7K 
[TXT]__5_2_8_12__0xN840_0xN843_32_Port_WRED_Queue_Control_Register_0.c2026-02-10 16:28 2.2K 
[TXT]__5_2_8_13__0xN844_0xN847_32_Port_WRED_Queue_Control_Register_1.c2026-02-10 16:28 2.4K 
[TXT]__5_2_8_14__0xN848_0xN84B_32_Port_WRED_Queue_Performance_Monitor_Control_Register.c2026-02-10 16:28 4.6K 
[TXT]__5_2_8__PORT_N_PORT_SWITCH_INGRESS_CONTROL_REGISTERS.c2026-02-10 16:28 252  
[TXT]__5_2_9_1__0xN900_0xN903_32_Port_Transmit_Queue_Index_Register.c2026-02-10 16:28 1.5K 
[TXT]__5_2_9_2__0xN904_0xN907_32_Port_Transmit_Queue_PVID_Register.c2026-02-10 16:28 1.9K 
[TXT]__5_2_9_3__0xN914_0xN914_08_Port_Transmit_Queue_Control_0_Register.c2026-02-10 16:28 3.6K 
[TXT]__5_2_9_4__0xN915_0xN915_08_Port_Transmit_Queue_Control_1_Register.c2026-02-10 16:28 2.2K 
[TXT]__5_2_9_5__0xN916_0xN917_16_Port_Transmit_Credit_Shaper_Control_0_Register.c2026-02-10 16:28 1.3K 
[TXT]__5_2_9_6__0xN918_0xN919_16_Port_Transmit_Credit_Shaper_Control_1_Register.c2026-02-10 16:28 1.3K 
[TXT]__5_2_9_7__0xN91A_0xN91B_16_Port_Transmit_Credit_Shaper_Control_2_Register.c2026-02-10 16:28 1.3K 
[TXT]__5_2_9_8__0xN920_0xN920_08_Port_Time_Aware_Shaper_Control_Register.c2026-02-10 16:28 3.2K 
[TXT]__5_2_9_9__0xN923_0xN923_08_Port_Time_Aware_Shaper_Event_Index_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_2_9_10__0xN924_0xN927_32_Port_Time_Aware_Shaper_Event_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_2_9__PORT_N_PORT_SWITCH_EGRESS_CONTROL_REGISTERS.c2026-02-10 16:28 252  
[TXT]__5_2_10_1__0xNA00_0xNA03_32_Port_Control_0_Register.c2026-02-10 16:28 2.2K 
[TXT]__5_2_10_2__0xNA04_0xNA07_32_Port_Control_1_Register.c2026-02-10 16:28 2.1K 
[TXT]__5_2_10__PORT_N_PORT_SWITCH_QUEUE_MANAGEMENT_CONTROL_REGISTERS.c2026-02-10 16:28 272  
[TXT]__5_2_11_1__0xNB00_0xNB00_08_Port_Control_2_Register.c2026-02-10 16:28 5.1K 
[TXT]__5_2_11_2__0xNB01_0xNB01_08_Port_MSTP_Pointer_Register.c2026-02-10 16:28 1.4K 
[TXT]__5_2_11_3__0xNB04_0xNB04_08_Port_MSTP_State_Register.c2026-02-10 16:28 2.7K 
[TXT]__5_2_11__PORT_N_PORT_SWITCH_ADDRESS_LOOKUP_CONTROL_REGISTERS.c2026-02-10 16:28 270  
[TXT]__5_2_12_1__0xNC00_0xNC01_16_Port_PTP_Receive_Latency_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_2_12_2__0xNC02_0xNC03_16_Port_PTP_Transmit_Latency_Register.c2026-02-10 16:28 1.2K 
[TXT]__5_2_12_3__0xNC04_0xNC05_16_Port_PTP_Asymmetry_Correction_Register.c2026-02-10 16:28 1.9K 
[TXT]__5_2_12_4__0xNC08_0xNC09_16_Port_PTP_Egress_Timestamp_for_Request_and_Delay_High_Word_Register.c2026-02-10 16:28 1.4K 
[TXT]__5_2_12_5__0xNC0A_0xNC0B_16_Port_PTP_Egress_Timestamp_for_Request_and_Delay_Low_Word_Register.c2026-02-10 16:28 1.4K 
[TXT]__5_2_12_6__0xNC0C_0xNC0D_16_Port_PTP_Egress_Timestamp_for_Sync_High_Word_Register.c2026-02-10 16:28 1.4K 
[TXT]__5_2_12_7__0xNC0E_0xNC0F_16_Port_PTP_Egress_Timestamp_for_Sync_Low_Word_Register.c2026-02-10 16:29 1.4K 
[TXT]__5_2_12_8__0xNC10_0xNC11_16_Port_PTP_Egress_Timestamp_for_PDelay_Resp_High_Word_Register.c2026-02-10 16:29 1.4K 
[TXT]__5_2_12_9__0xNC12_0xNC13_16_Port_PTP_Egress_Timestamp_for_PDelay_Resp_Low_Word_Register.c2026-02-10 16:29 1.4K 
[TXT]__5_2_12_10__0xNC14_0xNC15_16_Port_PTP_Timestamp_Interrupt_Status_Register.c2026-02-10 16:29 4.1K 
[TXT]__5_2_12_11__0xNC16_0xNC17_16_Port_PTP_Timestamp_Interrupt_Enable_Register.c2026-02-10 16:29 4.1K 
[TXT]__5_2_12_12__0xNC18_0xNC1B_32_Port_PTP_Link_Delay_Register.c2026-02-10 16:29 1.2K 
[TXT]__5_2_12__PORT_N_PORT_SWITCH_PTP_CONTROL_REGISTERS.c2026-02-10 16:28 246  
[TXT]__5_2__PORT_REGISTERS_OVERVIEW.c2026-02-10 16:28 636  
[TXT]__5_3_1_1__0x_____0x_____0_Address_Lookup_Table_Read_Operation.c2026-02-10 16:29 1.7K 
[TXT]__5_3_1_2__0x_____0x_____0_Address_Lookup_Table_Search_Operation.c2026-02-10 16:29 2.2K 
[TXT]__5_3_1_3__0x_____0x_____0_Address_Lookup_Table_Write_Operation.c2026-02-10 16:29 825  
[TXT]__5_3_1_4__0x0420_0x0423_32_ALU_Table_Entry_1_Register.c2026-02-10 16:29 3.9K 
[TXT]__5_3_1_5__0x0424_0x0427_32_ALU_Table_Entry_2_Register.c2026-02-10 16:29 2.3K 
[TXT]__5_3_1_6__0x0428_0x042B_32_ALU_Table_Entry_3_Register.c2026-02-10 16:29 1.6K 
[TXT]__5_3_1_7__0x042C_0x042F_32_ALU_Table_Entry_4_Register.c2026-02-10 16:29 943  
[TXT]__5_3_1__ADDRESS_LOOKUP_ALU_TABLE.c2026-02-10 16:29 5.1K 
[TXT]__5_3_2_1__0x_____0x_____0_Static_Address_Table_Write_Operation.c2026-02-10 16:29 911  
[TXT]__5_3_2_2__0x_____0x_____0_Static_Address_Table_Read_Operation.c2026-02-10 16:29 912  
[TXT]__5_3_2_3__0x0420_0x0423_32_Static_Address_Table_Entry_1_Register.c2026-02-10 16:29 3.2K 
[TXT]__5_3_2_4__0x0424_0x0427_32_Static_Address_Table_Entry_2_Register.c2026-02-10 16:29 2.8K 
[TXT]__5_3_2_5__0x0428_0x042B_32_Static_Address_Table_Entry_3_Register.c2026-02-10 16:29 1.6K 
[TXT]__5_3_2_6__0x042C_0x042F_32_Static_Address_Table_Entry_4_Register.c2026-02-10 16:29 955  
[TXT]__5_3_2__STATIC_ADDRESS_TABLE.c2026-02-10 16:29 1.2K 
[TXT]__5_3_3_1__0x_____0x_____0_Reserved_Multicast_Table_Write_Operation.c2026-02-10 16:29 798  
[TXT]__5_3_3_2__0x_____0x_____0_Reserved_Multicast_Table_Read_Operation.c2026-02-10 16:29 807  
[TXT]__5_3_3_3__0x0424_0x0427_32_Reserved_Multicast_Address_Table_Entry_2_Register.c2026-02-10 16:29 2.1K 
[TXT]__5_3_3__RESERVED_MULTICAST_ADDRESS_TABLE.c2026-02-10 16:29 1.1K 
[TXT]__5_3_4_1__VLAN_Table_Write_Operation.c2026-02-10 16:29 780  
[TXT]__5_3_4_2__VLAN_Table_Read_Operation.c2026-02-10 16:29 655  
[TXT]__5_3_4__VLAN_TABLE.c2026-02-10 16:29 4.5K 
[TXT]__5_3_5_1__ACL_Table_Read.c2026-02-10 16:29 685  
[TXT]__5_3_5_2__ACL_Table_Write.c2026-02-10 16:29 891  
[TXT]__5_3_5__ACCESS_CONTROL_LIST_ACL_TABLE.c2026-02-10 16:29 6.0K 
[TXT]__5_3_6_1__MIB_Counter_Read_Operation.c2026-02-10 16:29 1.2K 
[TXT]__5_3_6_2__MIB_Counter_Freeze_and_Flush_Functions.c2026-02-10 16:29 1.4K 
[TXT]__5_3_6__MANAGEMENT_INFORMATION_BASE_MIB_COUNTERS.c2026-02-10 16:29 9.3K 
[TXT]__5_3__TABLES_AND_MIB_COUNTERS_ACCESS.c2026-02-10 16:29 528  
[TXT]__5_4_1__0x01_0x02_16_MMD_Signal_Quality_Channel_A_Register.c2026-02-10 16:29 1.7K 
[TXT]__5_4_2__0x01_0x02_16_MMD_Signal_Quality_Channel_B_Register.c2026-02-10 16:29 1.7K 
[TXT]__5_4_3__0x01_0x02_16_MMD_Signal_Quality_Channel_C_Register.c2026-02-10 16:29 1.7K 
[TXT]__5_4_4__0x01_0x02_16_MMD_Signal_Quality_Channel_D_Register.c2026-02-10 16:29 1.7K 
[TXT]__5_4_5__0x02_0x03_16_MMD_LED_Mode_Register.c2026-02-10 16:29 1.7K 
[TXT]__5_4_6__0x07_0x08_16_MMD_EEE_Advertisement_Register.c2026-02-10 16:29 2.2K 
[TXT]__5_4_7__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_0_Register.c2026-02-10 16:29 958  
[TXT]__5_4_8__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_1_Register.c2026-02-10 16:29 958  
[TXT]__5_4_9__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_2_Register.c2026-02-10 16:29 958  
[TXT]__5_4_10__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_3_Register.c2026-02-10 16:29 960  
[TXT]__5_4_11__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_4_Register.c2026-02-10 16:29 960  
[TXT]__5_4_12__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_5_Register.c2026-02-10 16:29 960  
[TXT]__5_4_13__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_6_Register.c2026-02-10 16:29 960  
[TXT]__5_4_14__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_7_Register.c2026-02-10 16:29 960  
[TXT]__5_4_15__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_8_Register.c2026-02-10 16:29 960  
[TXT]__5_4_16__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_9_Register.c2026-02-10 16:29 960  
[TXT]__5_4_17__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_10_Register.c2026-02-10 16:29 962  
[TXT]__5_4_18__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_11_Register.c2026-02-10 16:29 962  
[TXT]__5_4_19__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_12_Register.c2026-02-10 16:29 962  
[TXT]__5_4_20__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_13_Register.c2026-02-10 16:29 962  
[TXT]__5_4_21__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_14_Register.c2026-02-10 16:29 962  
[TXT]__5_4_22__0x1C_0x1D_16_MMD_Quiet_Wire_Configuration_15_Register.c2026-02-10 16:29 962  
[TXT]__5_4__MDIO_MANAGEABLE_DEVICE_MMD_REGISTERS_INDIRECT.c2026-02-10 16:29 4.9K 
[TXT]__5_5_1__0x1F0000_16_SGMII_Control_Register.c2026-02-10 16:29 7.0K 
[TXT]__5_5_2__0x1F0001_16_SGMII_Status_Register.c2026-02-10 16:29 4.0K 
[TXT]__5_5_3__0x1F0002_16_SGMII_PHY_ID_1_Register.c2026-02-10 16:29 917  
[TXT]__5_5_4__0x1F0003_16_SGMII_PHY_ID_2_Register.c2026-02-10 16:29 917  
[TXT]__5_5_5__0x1F0004_16_SGMII_Auto_Negotiation_Advertisement_Register.c2026-02-10 16:29 5.4K 
[TXT]__5_5_6__0x1F0005_16_SGMII_Auto_Negotiation_Link_Partner_Base_Ability_Register.c2026-02-10 16:29 5.7K 
[TXT]__5_5_7__0x1F0006_16_SGMII_Auto_Negotiation_Expansion_Register.c2026-02-10 16:29 1.7K 
[TXT]__5_5_8__0x1F8000_16_SGMII_Digital_Control_Register.c2026-02-10 16:29 3.0K 
[TXT]__5_5_9__0x1F8001_16_SGMII_Auto_Negotiation_Control_Register.c2026-02-10 16:29 4.5K 
[TXT]__5_5_10__0x1F8002_16_SGMII_Auto_Negotiation_Status_Register.c2026-02-10 16:29 5.0K 
[TXT]__5_5__SGMII_Registers_Indirect.c2026-02-10 16:29 2.0K 
[TXT]_index.txt2026-02-11 14:38 75K